Skip to content

HAL_ChibiOS: raise SDMMC clock limit on H7 #26090

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
tridge merged 1 commit into from
Jan 28, 2024
Merged

HAL_ChibiOS: raise SDMMC clock limit on H7 #26090

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 2 additions & 3 deletions libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -633,10 +633,9 @@
// limit ISR count per byte
#define STM32_I2C_ISR_LIMIT 6

// limit SDMMC clock to 12.5MHz by default. This increases
// reliability
// limit SDMMC clock to 50MHz by default
#ifndef STM32_SDC_MAX_CLOCK
#define STM32_SDC_MAX_CLOCK 12500000
#define STM32_SDC_MAX_CLOCK 50000000
#endif

#ifndef STM32_WSPI_USE_QUADSPI1
Expand Down