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riscv: Add stimecmp CSR Check Labels #828: Pull request #419 synchronize by romancardenas
2m 46s sbutz:stimecmp
sbutz:stimecmp
2m 46s
riscv: add Sdtrig CSRs as raw usize accessors Check Labels #827: Pull request #413 synchronize by romancardenas
1m 4s JurajSadel:upstream/sdtrig-stubs
JurajSadel:upstream/sdtrig-stubs
1m 4s
riscv: Add stimecmp CSR Check Labels #826: Pull request #419 ready_for_review by sbutz
7s sbutz:stimecmp
sbutz:stimecmp
7s
riscv: Add stimecmp CSR Check Labels #825: Pull request #419 opened by sbutz
1m 53s sbutz:stimecmp
sbutz:stimecmp
1m 53s
riscv: use CSR immediate instructions for set_csr!/clear_csr! field masks Check Labels #824: Pull request #417 opened by XuanTongYao
3m 46s XuanTongYao:feat/set-clear-csr-uimm
XuanTongYao:feat/set-clear-csr-uimm
3m 46s
riscv: add Sdtrig CSRs as raw usize accessors Check Labels #823: Pull request #413 synchronize by JurajSadel
31s JurajSadel:upstream/sdtrig-stubs
JurajSadel:upstream/sdtrig-stubs
31s
riscv: extend raw bit access to the _as_usize CSR modules Check Labels #822: Pull request #416 synchronize by JurajSadel
40s JurajSadel:upstream/csr-raw-bits-as-usize
JurajSadel:upstream/csr-raw-bits-as-usize
40s
riscv: extend raw bit access to the _as_usize CSR modules Check Labels #821: Pull request #416 synchronize by JurajSadel
6s JurajSadel:upstream/csr-raw-bits-as-usize
JurajSadel:upstream/csr-raw-bits-as-usize
6s
riscv: add Sdtrig CSRs as raw usize accessors Check Labels #820: Pull request #413 synchronize by JurajSadel
47s JurajSadel:upstream/sdtrig-stubs
JurajSadel:upstream/sdtrig-stubs
47s
riscv: add raw bit access to generated CSR modules Check Labels #819: Pull request #415 synchronize by JurajSadel
9s JurajSadel:upstream/csr-raw-bits-typed
JurajSadel:upstream/csr-raw-bits-typed
9s
riscv: add misa write side Check Labels #818: Pull request #414 synchronize by JurajSadel
37s JurajSadel:upstream/misa-write
JurajSadel:upstream/misa-write
37s
riscv: add Sdtrig CSRs as raw usize accessors Check Labels #817: Pull request #413 synchronize by JurajSadel
9s JurajSadel:upstream/sdtrig-stubs
JurajSadel:upstream/sdtrig-stubs
9s
Add atomic topei read-clear operations Check Labels #816: Pull request #409 synchronize by KushalMeghani1644
6m 52s KushalMeghani1644:fix-408
KushalMeghani1644:fix-408
6m 52s
Add atomic topei read-clear operations Check Labels #815: Pull request #409 synchronize by KushalMeghani1644
1m 30s KushalMeghani1644:fix-408
KushalMeghani1644:fix-408
1m 30s
Add atomic topei read-clear operations Check Labels #814: Pull request #409 synchronize by KushalMeghani1644
25s KushalMeghani1644:fix-408
KushalMeghani1644:fix-408
25s
riscv: extend raw bit access to the _as_usize CSR modules Check Labels #813: Pull request #416 opened by JurajSadel
2m 7s JurajSadel:upstream/csr-raw-bits-as-usize
JurajSadel:upstream/csr-raw-bits-as-usize
2m 7s
riscv: add raw bit access to generated CSR modules Check Labels #812: Pull request #415 opened by JurajSadel
7m 49s JurajSadel:upstream/csr-raw-bits-typed
JurajSadel:upstream/csr-raw-bits-typed
7m 49s
riscv: add misa write side Check Labels #811: Pull request #414 opened by JurajSadel
16m 31s JurajSadel:upstream/misa-write
JurajSadel:upstream/misa-write
16m 31s
riscv: add Sdtrig CSRs as raw usize accessors Check Labels #810: Pull request #413 opened by JurajSadel
20m 13s JurajSadel:upstream/sdtrig-stubs
JurajSadel:upstream/sdtrig-stubs
20m 13s
riscv: generate Pmpcsr via csr! macro Check Labels #809: Pull request #411 opened by JurajSadel
51s JurajSadel:feat/pmpcsr-via-csr
JurajSadel:feat/pmpcsr-via-csr
51s
riscv: Add From<usize> and From<CSR> on csr! types Check Labels #808: Pull request #410 opened by JurajSadel
3m 46s JurajSadel:feat/csr-from-usize
JurajSadel:feat/csr-from-usize
3m 46s
Add atomic topei read-clear operations Check Labels #807: Pull request #409 synchronize by KushalMeghani1644
6m 27s KushalMeghani1644:fix-408
KushalMeghani1644:fix-408
6m 27s
Add atomic topei read-clear operations Check Labels #806: Pull request #409 opened by KushalMeghani1644
6s KushalMeghani1644:fix-408
KushalMeghani1644:fix-408
6s
feat(riscv): add sireg CSR Check Labels #805: Pull request #406 ready_for_review by sbutz
1m 38s sbutz:sireg
sbutz:sireg
1m 38s
feat(riscv): add sireg CSR Check Labels #804: Pull request #406 synchronize by sbutz
1m 9s sbutz:sireg
sbutz:sireg
1m 9s