harvard-architecture

MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for educational purposes and distributed for free under open-source licenses.

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Processing Unit with RISCV-32 / RISCV-64 / RISCV-128

MIPS32-based Cpu89 in verilog for Course 10022502 Project

An simple implementation of the Differentiable Neural Harvard Computer

Processing Unit with OpenRISC-32 / OpenRISC-64

16 Bit, multicore, unicycle processor for general purpose simulated in VHDL. Created as a tool for teaching computer architecture at Federal University of Piauí.

dosage is a 20bit single cycle RISC cpu based on harvard architecture

A custom-designed 16-bit microcoded CISC processor featuring a 64-opcode custom ISA, 16-bit datapath, 16-bit address space, dual register banks, a 48-bit horizontal microprogrammed control unit, custom ALU, stack support, memory-mapped I/O, and a custom assembler, designed and implemented entirely from scratch.

A Verilog implementation of an 8-bit MIPS processor

📟 32 bits CPU design

The Agent Meta-Language — a capability-safe language for agents that make agents. Public, source-visible, all rights reserved; dual-use safety, proof, and release boundaries still maturing.

Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor

Implementação didática de um processador de 16 bits multiciclo em Logisim, com arquitetura Harvard, 16 registradores, ULA, unidade de controle e memórias separadas para programa e dados.

A 32-bit Single-Cycle RV32I RISC-V Processor implemented in Verilog HDL, featuring a Harvard Architecture, modular datapath design, hardware Performance Counter Unit (PCU), and functional verification using Icarus Verilog and GTKWave.

16-bit RISC pipeline simulator made in System-C following the classic 5-stage approach: IF, ID, EX, MEM, WB

A 32-bit modified-Harvard processor in structural VHDL, running on a Lattice MachXO2. Complex operations are composed from simple ones: multiply and divide are software routines and cost zero gates.

VHDL implementation of a single-cycle Harvard-architecture processor based on the LEGv8 subset introduced by Hennessy and Patterson.

Implementing a subset of ARM instruction set architecture in a multicycle microarchitecture using Xilinx Vivado IDE. The computer architecture followed is Harvard.

C simulator for an 8-bit pipelined Harvard-architecture processor with assembly parsing, instruction encoding, hazard detection, and cycle-by-cycle execution tracing.