Maked intermediate additions unsigned in ModAdd

[fpapa250]

Replicate bug with ModAdd(bitsize=8, mod=17).adjoint().on_classical_vals(x=0,y=0). Basically, we do signed integer addition with registers that have unsigned dtypes. Change the intermediate register dtypes to QInt to perform modular reductions then restore to unsigned int dtypes.

[NoureldinYosri]

this is the only line that needs changing

Qualtran/qualtran/bloqs/mod_arithmetic/mod_addition.py

Line 118 in d661d69

y = bb.add(AddK(bitsize=self.bitsize + 1, k=-1 * self.mod, signed=True, cvs=()), x=y)

[fpapa250]

Both lines ended up needing changing; I tested it with the error showing up in my ECAdd PR.

[NoureldinYosri]

Both lines ended up needing changing; I tested it with the error showing up in my ECAdd PR.

yea, makes sense that all additions are unsigned