Taking place in the final phase of the project (last three months), this task focuses on preparing a comprehensive technical publication describing the openENOC architecture, implementation, and validation results.
The publication synthesizes outcomes from all preceding work packages, including the RTL implementation, software stack, verification infrastructure, FPGA demonstration platforms, and open-source synthesis and PnR flows. It presents both the architectural principles and the practical realization of an Ethernet-based Network-on-Chip for MPSoC systems.
Particular emphasis is placed on the system-level integration of heterogeneous datapaths, multi-clock operation, and the end-to-end hardware/software stack. The publication aims to provide a clear and reproducible reference for researchers and practitioners working in open hardware, NoC architectures, and FPGA-based system design.
The outcome of DIS1 is a peer-review-ready technical paper suitable for submission to relevant open hardware, FPGA, or systems conferences and/or journals.
Taking place in the final phase of the project (last three months), this task focuses on preparing a comprehensive technical publication describing the openENOC architecture, implementation, and validation results.
The publication synthesizes outcomes from all preceding work packages, including the RTL implementation, software stack, verification infrastructure, FPGA demonstration platforms, and open-source synthesis and PnR flows. It presents both the architectural principles and the practical realization of an Ethernet-based Network-on-Chip for MPSoC systems.
Particular emphasis is placed on the system-level integration of heterogeneous datapaths, multi-clock operation, and the end-to-end hardware/software stack. The publication aims to provide a clear and reproducible reference for researchers and practitioners working in open hardware, NoC architectures, and FPGA-based system design.
The outcome of DIS1 is a peer-review-ready technical paper suitable for submission to relevant open hardware, FPGA, or systems conferences and/or journals.