[Wasm RyuJIT] Codegen for Const Vector Create and Basic Packed SIMD operations#129703
Open
adamperlin wants to merge 18 commits into
Open
[Wasm RyuJIT] Codegen for Const Vector Create and Basic Packed SIMD operations#129703adamperlin wants to merge 18 commits into
adamperlin wants to merge 18 commits into
Conversation
Enable Wasm SIMD ISA for use in the JIT
…simd, simd) param type operations (no integer operands or immediates supported yet)
Contributor
|
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
Contributor
There was a problem hiding this comment.
Pull request overview
This PR extends CoreCLR’s Wasm (RyuJIT) pipeline to recognize Wasm SIMD instruction-set support and begin emitting v128 SIMD code, including constant Vector128.Create lowering to v128.const and table-driven codegen for many PackedSimd operations.
Changes:
- Enable Wasm ISA flags (
WasmBase,PackedSimd,Vector128) and wire up instruction-set support for Wasm32 (base,simd128). - Add
GT_CNS_VECemission viav128.const, plus v128 load/store selection forTYP_SIMD16. - Introduce initial importer/list/codegen plumbing for
PackedSimdandVector128.Createconstants.
Reviewed changes
Copilot reviewed 13 out of 13 changed files in this pull request and generated 6 comments.
Show a summary per file
| File | Description |
|---|---|
| src/libraries/System.Private.CoreLib/src/System.Private.CoreLib.Shared.projitems | Enables SupportsWasmIntrinsics for CoreCLR Wasm builds. |
| src/coreclr/tools/Common/InstructionSetHelpers.cs | Adds Wasm32 baseline instruction sets (base, simd128). |
| src/coreclr/jit/lowerwasm.cpp | Starts allowing SIMD-category GT_HWINTRINSIC through lowering. |
| src/coreclr/jit/lower.cpp | Relaxes TYP_SIMD12 assert for Wasm during lowering checks. |
| src/coreclr/jit/instr.cpp | Adds Wasm v128_load/v128_store mapping for TYP_SIMD16. |
| src/coreclr/jit/hwintrinsicwasm.cpp | Implements constant Vector128.Create import to GT_CNS_VEC. |
| src/coreclr/jit/hwintrinsiclistwasm.h | Adds PackedSimd intrinsic definitions and updates some Vector128 entries. |
| src/coreclr/jit/hwintrinsiccodegenwasm.cpp | Adds initial table-driven Wasm HW intrinsic emission. |
| src/coreclr/jit/hwintrinsic.h | Adds a Wasm HWIntrinsic helper wrapper (but currently has a preprocessor issue). |
| src/coreclr/jit/hwintrinsic.cpp | Adds Wasm PackedSimd ISA range and simdSize validation for Wasm. |
| src/coreclr/jit/compiler.cpp | Forces Wasm baseline ISAs into JIT supported set, adds Vector128. |
| src/coreclr/jit/codegenwasm.cpp | Adds GT_HWINTRINSIC dispatch and GT_CNS_VEC emission (v128.const). |
| src/coreclr/jit/codegen.h | Declares Wasm vector-constant codegen helper. |
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
…case in SPMI (can happen if NYI_WASM_SIMD fires during import)
adamperlin
commented
Jun 23, 2026
Comment on lines
18
to
20
| <SupportsWasmIntrinsics Condition="'$(Platform)' == 'wasm' and '$(FeatureMono)' == 'true'">true</SupportsWasmIntrinsics> | ||
| <SupportsWasmIntrinsics Condition="'$(Platform)' == 'wasm' and '$(FeatureCoreCLR)' == 'true'">true</SupportsWasmIntrinsics> | ||
| <SupportsWasmIntrinsics Condition="'$(SupportsWasmIntrinsics)' == ''">false</SupportsWasmIntrinsics> |
Comment on lines
+68
to
+72
| #define FIRST_NI_PackedSimd NI_PackedSimd_Abs | ||
| HARDWARE_INTRINSIC(PackedSimd, Abs, 16, 1, {INS_i8x16_abs, INS_invalid, INS_i16x8_abs, INS_invalid, INS_i32x4_abs, INS_invalid, INS_i64x2_abs, INS_invalid, INS_f32x4_abs, INS_f64x2_abs}, HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg) | ||
| HARDWARE_INTRINSIC(PackedSimd, Add, 16, 2, {INS_i8x16_add, INS_i8x16_add, INS_i16x8_add, INS_i16x8_add, INS_i32x4_add, INS_i32x4_add, INS_i64x2_add, INS_i64x2_add, INS_f32x4_add, INS_f64x2_add}, HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_Commutative) | ||
| HARDWARE_INTRINSIC(PackedSimd, AddPairwiseWidening, 16, 1, {INS_i16x8_extadd_pairwise_s_i8x16, INS_i16x8_extadd_pairwise_u_i8x16, INS_i32x4_extadd_pairwise_s_i16x8, INS_i32x4_extadd_pairwise_u_i16x8, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg) | ||
| HARDWARE_INTRINSIC(PackedSimd, AddSaturate, 16, 2, {INS_i8x16_add_sat_s, INS_i8x16_add_sat_u, INS_i16x8_add_sat_s, INS_i16x8_add_sat_u, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_Commutative) |
AndyAyersMS
reviewed
Jun 23, 2026
AndyAyersMS
left a comment
Member
There was a problem hiding this comment.
I don't have anything to add over what copilot has pointed out.
I'll take another look when you've sorted through that; ping me.
This was referenced Jun 23, 2026
Open
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
Comment on lines
+1819
to
+1828
| void CodeGen::genCodeForVectorConstant(GenTree* treeNode) | ||
| { | ||
| assert(treeNode->IsCnsVec()); | ||
| GenTreeVecCon* vecCon = treeNode->AsVecCon(); | ||
|
|
||
| // There is only one type variant for v128.const, v128.const <byte[16]> | ||
| // and the bytes are reinterpreted according to whichever operation consumes the value. | ||
| GetEmitter()->emitIns_V128Imm(INS_v128_const, vecCon->gtSimd16Val.u8); | ||
| WasmProduceReg(treeNode); | ||
| } |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
This PR implements support for
Vector128.Createon Wasm with known constant args, as well as table-driven expansion and codegen for a large set of PackedSimd opcodes that operate on v128, (v128, v128) and (v128, v128, v128) type operands.Notably absent from this PR: Vector128.Create with non-constants (requires additional lowering work), and SIMD compares (need special codegen for ulong since i64_u compare is not natively supported on Wasm).