Search results

FW Disable of Virtual Target

Future

Status: Open.

Feature

#224 In chipsalliance/i3c-core;

· clayton8 opened on Jul 21, 2026

Add Locks to PID Registers

Future

Status: Open.

Feature

#223 In chipsalliance/i3c-core;

· clayton8 opened on Jul 20, 2026

I3C GETMRL Return Data

Future

Status: Open.

Feature

#222 In chipsalliance/i3c-core;

· clayton8 opened on Jul 15, 2026

I3C GETSTATUS Format Handling

Future

Status: Open.

Feature

#221 In chipsalliance/i3c-core;

· clayton8 opened on Jul 15, 2026

PROT_ERROR for I3C writes to RECOVERY_STATUS

Future

Status: Open.

Feature

#220 In chipsalliance/i3c-core;

· clayton8 opened on Jul 15, 2026

[v1p5] Potential bug when switching between virtual and main targets

Test-Env-IssueTest fixes or environment (tools, reference modes) fixesTest fixes or environment (tools, reference modes) fixes

Status: Open.

Task

#207 In chipsalliance/i3c-core;

· PiotrZierhoffer opened on May 12, 2026

Sync Reset Support

Future

Status: Open.

Feature

#76 In chipsalliance/i3c-core;

· clayton8 opened on Oct 27, 2025

[PIO CSR] Access PIO reg 0x84 will cause bus to hang up

Future

Status: Open.

#64 In chipsalliance/i3c-core;

· nelson-ou opened on Sep 10, 2025

Make recovery target for RSTACT CCC configurable

Future

Status: Open.

Feature

#62 In chipsalliance/i3c-core;

· tmichalak opened on Sep 2, 2025

File/Module name conflict

Status: Open.

#49 In chipsalliance/i3c-core;

· morris-c-mao opened on Aug 7, 2025

RAL model for I3C Register map

enhancementNew feature or requestNew feature or request

Status: Open.

#30 In chipsalliance/i3c-core;

· nileshbpat opened on Mar 31, 2025