v1.4.2

v1.4.2

🧠 TL;DR

• ✅ ObjectFIFOs are now fully dynamic, with simplified lowering and lock allocation
• ✅ Expanded DMA capabilities, verification, and runtime-sequence support
• ✅ Improved HostRuntime efficiency and HRX stability
• ✅ New AIE2P kernels and continued compiler, build, and CI improvements

🔍 Highlights

🧩 ObjectFIFO & DMA

• Made ObjectFIFOs fully dynamic, removing custom unrolling from ObjectFIFO lowering in favor of a reusable unrolling pass and separating lock ID allocation from the ObjectFIFO transformation → @andrej
• Added BD iteration support to aie.dma_bd and out-of-order S2MM DMA receive channels → @jskimko
• Improved DMA correctness with expanded BD verification and more efficient dynamic BD programming through a single block write → @xhmelon, @hunhoffe

⚡ Runtime, Compiler & Kernels

• Improved HostRuntime efficiency by opening the NPU once per process rather than once per tensor, and fixed an HRX run_chain use-after-free → @Abhishek-Varma
• Added three new AIE2P kernels and extended layer_norm, alongside additional AIEVec lowering support → @atassis, @erwei-xilinx
• Improved placement, runtime-sequence handling, Peano compatibility, and added an AIECC_PATH override for compiler discovery → @erwei-xilinx, @hunhoffe, @atassis

🛠️ Build, CI & Developer Experience

• Added clang-tidy and continued dependency and build-system modernization → @hunhoffe
• Fixed AArch64 wheel linking and improved self-hosted CI scheduling, timeouts, and code-coverage workflows → @hunhoffe, @atassis
• Updated aie-rt and added automated dependency tracking for future updates → @hunhoffe

🔭 Looking Ahead

Several programming-model areas remain under active development and may continue to evolve in upcoming releases:

• Continued consolidation of DMA lowering and verification may introduce API changes or deprecation around npu.dma_memcpy_nd.
• ObjectFIFO APIs and lowering will continue evolving as part of ongoing restructuring efforts.
• The IRON Python APIs will continue expanding toward more ergonomic dynamic runtime-sequence generation and host-driven execution.

Thank you to everyone who contributed to the v1.4.2 release!

v1.4.1

v1.4.1

🧠 TL;DR

• ✅ Expanded HostRuntime with NpuTensor, sub-region views, and explicit storage
• ✅ Peano is now the default AIE core backend, with improved LLVM compatibility
• ✅ More robust IRON kernel inlining, JIT caching, and host-runtime infrastructure
• ✅ Improved tracing, routing, DMA correctness, and compiler diagnostics
• ✅ Stronger Windows support, CI coverage, and Python developer tooling

🔍 Highlights

🧩 IRON & Host Runtime

• Expanded the Python HostRuntime with NpuTensor, sub-region views, and explicit Storage, providing a richer foundation for host-side NPU memory management → @atassis
• Improved IRON external-kernel inlining by merging LLVM IR in-process before Peano downgrade, making the inline compilation path introduced in v1.4 more robust → @fifield
• Strengthened JIT cache correctness by validating recorded dependency manifests, ensuring cached artifacts are invalidated when their compilation dependencies change → @atassis
• Unified HRX and XRT hardware test infrastructure around a runtime-agnostic NPU test suite → @Abhishek-Varma
• Fixed Windows XRTKernelResult.run NPU timing precision → @astrelsky

⚙️ Compiler & Peano

• Peano is now the default core backend in aiecc, continuing the transition away from Chess for standard compilation flows → @atassis
• Improved Peano compatibility following the LLVM 24 transition, including narrow-float literal handling, arithmetic min/max lowering, and preservation of module alignment → @erwei-xilinx
• Fixed legal start-column selection for virtualized NPU partitions and improved column-control overlay generation → @atassis
• Moved additional device-specific behavior, including default core stack size, into AIETargetModel and strengthened handling of invalid target devices → @atassis
• Improved build diagnostics by validating Peano installation paths and backend directories early instead of failing later in compilation → @atassis

🛡️ DMA, Routing & Correctness

• Improved DMA robustness with safer verification of BD dimensions, target-aware reset register resolution, and better handling of unplaced tiles → @atassis
• Wired DMA pad_value through to hardware and moved its representation to the DMA channel → @jskimko
• Fixed packet-flow channel sharing and now fail compilation when packet-flow routing is incomplete → @andrej, @jskimko
• Added hardware coverage for routing multiple flows with the same packet ID → @erwei-xilinx
• Fixed AIEVec signedness handling through vector.contract lowering, including consistent semantics for signless matmul operands → @erwei-xilinx
• Fixed runtime ELF loading to correctly zero the p_memsz - p_filesz region of PT_LOAD segments → @hunhoffe

📡 Tracing & AIE2P

• Added core EVENT_PC tracing mode for program-counter-based event tracing → @FIM43-Redeye
• Improved core-memory event activation when tracing individual tiles → @atassis
• Expanded trace coverage for bf16 single-core matmul configurations → @hunhoffe
• Added an AIE2P matrix-multiply activation epilogue supporting three RTP-selected GEMM epilogues from a single xclbin → @atassis

🪟 Windows, Build & CI

• Expanded Windows CI to build from wheels and smoke-test produced packages, with Peano nightlies now required to provide wheels for every supported CI platform → @jgmelber
• Improved build scalability with configurable parallelism and more reliable ccache integration → @jskimko, @atassis
• Improved on-device CI reliability and throughput through finer-grained device locking, targeted transient-failure retries, and reduced redundant NPU testing → @atassis, @jgmelber
• Added diff coverage reporting, PR-time documentation validation, and broader wheel/test coverage to catch regressions earlier → @hunhoffe
• Moved GitHub-hosted CI away from the deprecated Ubuntu 22.04 runner image → @hunhoffe

🛠️ Developer Experience

• Added Ruff linting and expanded Ruff/Pyright coverage across programming examples, including consistent docstring-style enforcement → @hunhoffe
• Improved test metadata by explicitly identifying each test's backend and moving tests away from Chess where it is no longer required → @atassis
• Improved documentation deployment reliability and added the ROCm-NPU Discord channel to the project documentation → @hunhoffe

⚠️ Migration Notes

This release continues several transitions introduced in v1.4.0. Most users should be able to upgrade without major changes, but downstream projects should be aware of the following:

• Peano is now the default AIE core backend in aiecc. Workflows that implicitly relied on Chess should explicitly select the required backend or migrate to Peano where possible.
• Target validation is stricter. Requests for unknown AIEDevice values now produce an error instead of silently falling back to the VC1902 target model.
• Packet-flow routing is more strictly validated. Incomplete packet-flow routing now fails compilation instead of allowing an incomplete configuration to proceed.
• DMA verification is stricter. Malformed or inconsistent DMA BD dimension lists that may previously have progressed further through compilation are now diagnosed earlier.

🔭 Looking Ahead

Several programming-model areas remain under active development and may continue to evolve in upcoming releases:

• Continued consolidation of DMA lowering and verification may introduce API changes or deprecation around npu.dma_memcpy_nd.
• ObjectFIFO APIs and lowering are expected to evolve as part of ongoing ObjectFIFO restructuring.
• The IRON Python APIs will continue expanding toward more ergonomic, dynamic runtime-sequence generation and host-driven execution.

🙌 New Contributors

A warm welcome to our first-time contributor!

• @astrelsky

Thank you to everyone who contributed to the v1.4.1 release!

v1.4.0

v1.4.0

🧠 TL;DR

• ✅ Major expansion of dynamic runtime sequences for expressive host-driven execution
• ✅ New HRX (amdxdna) Host Runtime backend and improved full-ELF deployment workflows
• ✅ Faster IRON execution with optional kernel inlining and improved JIT infrastructure
• ✅ Stronger compiler verification, ObjectFIFO analysis, and DMA correctness
• ✅ Continued compiler modernization, documentation, and Windows support

🔍 Highlights

🚀 Dynamic Runtime Sequences

Dynamic runtime sequences take a major step forward in this release, enabling significantly more expressive host-controlled execution.

• Added dynamic SSA-based runtime sequence operands, dynamic DMA descriptors, runtime BD allocation, dynamic conditionals, and runtime tracing support → @hunhoffe
• Added C++ TXN generation, dynamic BD-word encoding, an equivalence test harness validating static and dynamic execution, and an example fully dynamic multi-column GEMM with runtime-configurable problem sizes → @hunhoffe, @jgmelber
• Added new runtime-sequence operations including DMA channel reset, DMA channel reset loops, and core reset support → @atassis

🧩 IRON & Host Runtime

• Introduced the new HRX (amdxdna) Host Runtime backend, enabling XRT-free deployment and xclbin packaging → @Abhishek-Varma
• Added optional kernel inlining for ExternalFunction, allowing C++ kernels to be linked directly into aie.core instead of being invoked via func.call, reducing call overhead and improving tight-loop performance by up to 2× → @fifield
• Added full-ELF support to iron.jit and XRTHostRuntime, exposing generated PDI artifacts and improving host-driven deployment workflows → @hunhoffe
• Added support for pinning L1 buffers and ObjectFIFO DMA channels for host-driven applications → @hunhoffe
• Enabled dynamic lock acquisition inside ObjectFIFO acquire/release operations and added support for control-packet-based device configuration as a drop-in alternative to load_pdi → @andrej

⚙️ Compiler Infrastructure

• Added support for more than five host buffers in aiecc, removing a long-standing full-ELF limitation and fixing associated segmentation faults → @hunhoffe, @erwei-xilinx
• Introduced a declarative rewrite of aiecc, parallel execution infrastructure, and declarative simulation flows to improve maintainability and compilation performance → @andrej
• Improved compiler scalability, routing performance, memory placement, and JIT cache correctness through numerous infrastructure improvements → @atassis, @jgmelber, @w3lld1

🛡️ Verification & Correctness

Compiler diagnostics and verification have been substantially strengthened, allowing more invalid programs to be detected before deployment.

• Added verification for DMA buffer descriptor limits, runtime-sequence deadlocks, DMA channel reset correctness, ObjectFIFO liveness, and placement-related failures → @atassis, @hunhoffe, @xhmelon
• Improved diagnostics for unplaced tiles and strengthened validation throughout the lowering pipeline → @atassis, @hunhoffe
• Improved correctness across AIE2 kernels, routing, JIT execution, and runtime behavior through numerous bug fixes from multiple contributors

📚 Documentation & Developer Experience

• Published HostRuntime Python API documentation and comprehensive runtime-sequence references → @ColumbusLabs, @atassis
• Added Agentic Programming documentation, refreshed the project roadmap, expanded community pages, and improved website organization → @hunhoffe, @erwei-xilinx
• Improved Windows installation, setup scripts, and added Windows CI support for Ryzen AI development → @thomthehound, @jgmelber
• Expanded the IRON programming skill chain, refreshed programming examples, and improved developer documentation throughout the project → @hunhoffe, @thomthehound

🧹 Platform Modernization

• Removed legacy ADF infrastructure, deprecated AIE1/Chess tutorials, obsolete runtime support, and other unmaintained components → @hunhoffe, @jgmelber
• Continued migration to upstream Xilinx and ROCm repositories for core dependencies and toolchains → @jgmelber
• Modernized CI with improved retry logic, dependency management, wheel validation, cache efficiency, and reliability across supported platforms → @hunhoffe, @andrej, @atassis

⚠️ Migration Notes

This release includes several programming model updates that may require downstream projects to be updated.

• Dynamic runtime sequences now use SSA operands throughout the compiler. Runtime sequence scalar values and DMA descriptor fields (sizes, strides, offsets, and lengths) have transitioned from attributes toward SSA values as part of the dynamic runtime sequence infrastructure.
• The IRON Runtime has been reworked around an eager callback execution model. Existing Python runtime sequence generation code may require updates to match the new execution model.
• TileDMA packet headers are now represented as explicit dma_bd_packet operations rather than attributes, improving compiler analysis and verification.
• Compiler verification is stricter. Programs with invalid ObjectFIFO usage, DMA configuration, runtime-sequence behavior, or placement issues that previously compiled may now produce diagnostic errors instead.

🔭 Looking Ahead

Development continues in several areas that are expected to evolve over upcoming releases:

• Continued consolidation of DMA lowering and verification may introduce API refinements to npu.dma_memcpy_nd.
• ObjectFIFO APIs and lowering will continue evolving as part of ongoing restructuring efforts.
• The IRON Python APIs will continue expanding to make dynamic runtime sequence generation more expressive, ergonomic, and host-centric.
• Native Windows development experience improvements, CI enhancements, build infrastructure, deprecation of WSL-based build processes.

🙌 New Contributors

A warm welcome to our first-time contributors!

• @xynexus
• @ColumbusLabs
• @xhmelon
• @jskimko
• @w3lld1

Thank you to everyone who contributed to the v1.4.0 release!

rocm-mlir-distro

MLIR wheels built from ROCm/llvm-project @ 46fcb339. Linux x86_64 only; Windows builds pending ccache fix (PR #3313).

v1.3.4

🧠 TL;DR

• ✅ Faster compiler and routing performance
• ✅ Continued Peano compatibility and testing improvements
• ✅ Cleaner IRON programming model and ObjectFifo defaults
• ✅ Improved JIT reliability and Python packaging
• ✅ Ongoing CI, dependency, and infrastructure modernization

🔍 Highlights

⚡ Compiler Performance & Scalability

• Improved compiler scalability by building per-core compile slices from a stripped base module and adopting a shared thread pool for core compilation → @atassis, @jgmelber
• Accelerated routing with dense integer vertex IDs in the Pathfinder router and reduced AIEX memref deduplication from linear to constant time → @jgmelber, @atassis
• Improved compiler parallelism by automatically selecting the number of compilation threads based on available CPUs → @jgmelber

🧩 IRON & Programming Model

• Moved tile placement validation into the compiler, simplifying the IRON tile API while providing earlier error checking → @hunhoffe
• Fixed unsafe cleanup of cached JIT artifacts in the DMA compression flow → @thomthehound

🔧 Peano & Compiler Compatibility

• Continued Peano enablement with expanded lit test coverage and automated version management → @thomthehound, @hunhoffe
• Improved compatibility with LLVM 23 by automatically downgrading newer floating-point and bfloat16 literal forms for Peano toolchains → @erwei-xilinx

🧹 Codebase Modernization, Build, Packaging, & CI

• Removed legacy/obsolete AIE/AIEX dialect operations, legacy AIEVec-to-C++ backend, legacy test suites, and unused Python files as part of continued codebase cleanup → @hunhoffe @jsetoain, @jgmelber
• Improved CI with automated Peano version pinning, lockfile validation, and license header enforcement → @hunhoffe, @andrej
• Updated CMake, nanobind, notebook, GitHub Actions, and other development dependencies to current supported versions → @dependabot, @jgmelber

v1.3.3

v1.3.3

🧠 TL;DR

• ✅ Enhanced IRON JIT workflow and DMA programming capabilities
• ✅ New simulated annealing AIE placer
• ✅ Faster compiler performance and improved Peano support
• ✅ Better Windows, packaging, and Python developer experience
• ✅ CI, build, and documentation improvements

🔍 Highlights

🧩 IRON & Programming Model

• Added multi-dimensional DMA strides (Bd.dimensions) and cross-core L1 buffer sharing for more expressive IRON programming → @hunhoffe
• Unified the @iron.jit compilation workflow across all programming examples and improved JIT caching by binding the target device before compilation → @hunhoffe, @thomthehound

📍 Placement & Compilation

• Added a new simulated annealing-based AIE placer for improved placement exploration → @yenjames
• Reduced compiler compile times by eliminating quadratic symbol lookups during NPU lowering → @atassis
• Improved aiecc lowering for full-ELF compilation and strengthened Peano compatibility and testing → @atassis, @erwei-xilinx, @thomthehound

⚡ Runtime & Platform Support

• Fixed Windows crashes in the Python XRT cached runtime → @thomthehound

🛠️ Developer Experience

• Added Pyright type checking across the Python codebase → @hunhoffe
• Added an aie-kernel-opt skills collection and expanded Linux build documentation for non-Ubuntu and in-tree amdxdna configurations → @hunhoffe, @AndreNijman

🐛 Build, CI & Stability

• Updated GitHub Actions dependencies, self-hosted runner configuration, and LLVM nightly pinning for improved CI stability → @dependabot, @andrej, @atassis, @hunhoffe

🙌 New Contributors

• @atassis
• @AndreNijman

v1.3.2

v1.3.2

🧠 TL;DR

• ✅ New AIE placement infrastructure and unplaced IRON workflows
• ✅ Tracing improvements and declarative trace APIs
• ✅ Expanded ObjectFifo and DMA functionality
• ✅ Improved AIE2/AIEVec lowering and kernel correctness
• ✅ Better NPU2, Windows, and packaging support
• ✅ Broad runtime, routing, and stability fixes

🔍 Highlights

🧩 Placement & IRON

• Introduced new AIE placement pass with flow-, memory-, and route-aware placement → @yenjames, @erwei-xilinx
• Continued migration to unplaced IRON; deprecated sequential placer → @yenjames, @hunhoffe

📡 Tracing & Runtime

• Added declarative trace APIs and improved trace routing/configuration → @yenjames, @FIM43-Redeye @fifield
• Enabled dynamic ObjectFifo lowering, DMA repeat-count support, and expanded ObjectFifo capabilities → @AndraBisca, @yenjames @hunhoffe

⚡ AIE2 & Performance

• Expanded AIEVec/AIE2P lowering support and bf16 optimizations → @erwei-xilinx
• Fixed AIE2 matmul correctness and enabled vectorized matvec kernels → @hunhoffe

🚀 Examples & Platform Support

• Ported MobileNet to IRON and expanded NPU2 support → @hunhoffe, @yenjames
• Added Python ELF and custom DMA examples → @andrej, @yenjames

🐛 Build, Packaging & Stability

• Improved Windows wheel packaging and PyPI readiness → @thomthehound, @hunhoffe
• LLVM/toolchain updates, CI modernization, and supply-chain hardening → @hunhoffe
• Numerous fixes across DMA, routing, ObjectFifos, runtime, and build systems → multiple contributors

🙌 New Contributors

• @FIM43-Redeye

latest-wheels-4

Switch from `latest-wheels-3` to `latest-wheels-4` (#3147)

latest-wheels-no-rtti-2

Bump cmake from 3.27.9 to 4.3.2 in /utils/mlir_wheels (#3080)

Signed-off-by: dependabot[bot] <support@github.com>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>

v1.3.1

What's Changed

• Flaky CI Fixes: Add retry policy for downloads and vendor eudsl-python-extras to reduce susceptibility to transient GitHub 502 failures.
• AIE Core To Standard Fixes: Set conv_even rounding mode for bf16 matmul and fix AIE2P control register indices for saturation and rounding.
• Miscellaneous Fixes: Fix xclbin UUIDs, non-deterministic crash in RunOp::verify(), and remove is_placed flag from JIT decorator.
• Peano Optimization Issue Resolved: Workaround flags for Peano -O2 issue removed.
• Pre-push Hook Added: Pre-push hook implemented for the repository.
• Mobilenet v3 Example Added: Design example for Mobilenet v3 included.

Full Changelog: v1.3.0...v1.3.1