CR-1000 : syncing files from GITE to GITHub by sabarinaxil · Pull Request #845 · Xilinx/XilinxBoardStore

sabarinaxil · 2026-08-11T05:52:09Z

No description provided.

github-actions · 2026-08-11T05:53:26Z

🔍 Board Pre-Validation Report

✅ All pre-validation checks passed before merge

Every board file in this pull request passed the automated checks. A reviewer may now proceed with the technical review.

1.1 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "scu200"
✔️ board.xml: display_name = "Spartan Ultrascale+ SCU200 Evaluation Platform"
✔️ board.xml: <file_version> = 1.1
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xcsu200p-sbva1024-2-e"
✔️ part0_pins.xml: 199 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 13 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "scu200"
✔️ xitem.json: infra.display = "Spartan Ultrascale+ SCU200 Evaluation Platform"
✔️ xitem.json: infra.revision = "1.1"
✔️ xitem.json: infra.description = "Spartan Ultrascale+ SCU200 Evaluation Platform"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

1.0 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "scu200_p"
✔️ board.xml: display_name = "Spartan Ultrascale+ SCU200(Rev B) Evaluation Platform"
✔️ board.xml: <file_version> = 1.0
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xcsu200p-sbva1024-2-e"
✔️ part0_pins.xml: 199 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 13 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "scu200_p"
✔️ xitem.json: infra.display = "Spartan Ultrascale+ SCU200(Rev B) Evaluation Platform"
✔️ xitem.json: infra.revision = "1.0"
✔️ xitem.json: infra.description = "Spartan Ultrascale+ SCU200(Rev B) Evaluation Platform"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

1.1 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "vek385"
✔️ board.xml: display_name = "VEK385 Evaluation Platform (Rev A)"
✔️ board.xml: <file_version> = 1.1
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xc2ve3858-ssva2112-2MP-e-S"
✔️ part0_pins.xml: 338 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 15 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "vek385"
✔️ xitem.json: infra.display = "Versal VEK385 Evaluation Platform"
✔️ xitem.json: infra.revision = "1.1"
✔️ xitem.json: infra.description = "Versal VEK385 Evaluation Platform"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

1.0 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "vek385_1"
✔️ board.xml: display_name = "VEK385 Evaluation Platform (Rev B)"
✔️ board.xml: <file_version> = 1.0
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xc2ve3858-ssva2112-2MP-e-S"
✔️ part0_pins.xml: 338 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 15 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "vek385_1"
✔️ xitem.json: infra.display = "Versal VEK385 Evaluation Platform (Rev B)"
✔️ xitem.json: infra.revision = "1.0"
✔️ xitem.json: infra.description = "Versal VEK385 Evaluation Platform (Rev B)"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

1.0 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "vek386"
✔️ board.xml: display_name = "VEK386 Evaluation Platform"
✔️ board.xml: <file_version> = 1.0
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xc2ve3858-ssva2397-2MP-e-S"
✔️ part0_pins.xml: 338 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 15 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "vek386"
✔️ xitem.json: infra.display = "Versal VEK386 Evaluation Platform"
✔️ xitem.json: infra.revision = "1.0"
✔️ xitem.json: infra.description = "Versal VEK386 Evaluation Platform"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

1.1 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "vpk360"
✔️ board.xml: display_name = "VPK360 Evaluation Platform"
✔️ board.xml: <file_version> = 1.1
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xc2vp3602-vsvc3340-2MP-e-S"
✔️ part0_pins.xml: 345 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 15 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "vpk360"
✔️ xitem.json: infra.display = "Versal VPK360 Evaluation Platform"
✔️ xitem.json: infra.revision = "1.1"
✔️ xitem.json: infra.description = "Versal VPK360 Evaluation Platform"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

1.0 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "vrk160"
✔️ board.xml: display_name = "VRK160 ES1 Evaluation Platform"
✔️ board.xml: <file_version> = 1.0
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xcvr1602-vsva2488-2MP-e-S-es1"
✔️ part0_pins.xml: 290 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 9 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "vrk160"
✔️ xitem.json: infra.display = "Versal VRK160 ES1 Evaluation Platform"
✔️ xitem.json: infra.revision = "1.0"
✔️ xitem.json: infra.description = "Versal VRK160 ES1 Evaluation Platform"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

1.1 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "vrk160"
✔️ board.xml: display_name = "VRK160 ES1 Evaluation Platform"
✔️ board.xml: <file_version> = 1.1
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xcvr1602-vsva2488-2MP-e-S-es1"
✔️ part0_pins.xml: 290 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 13 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "vrk160"
✔️ xitem.json: infra.display = "Versal VRK160 ES1 Evaluation Platform"
✔️ xitem.json: infra.revision = "1.1"
✔️ xitem.json: infra.description = "Versal VRK160 ES1 Evaluation Platform"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

1.2 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "vrk160"
✔️ board.xml: display_name = "VRK160 ES1 Evaluation Platform"
✔️ board.xml: <file_version> = 1.2
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xcvr1602-vsva2488-2MP-e-S-es1"
✔️ part0_pins.xml: 290 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 13 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "vrk160"
✔️ xitem.json: infra.display = "Versal VRK160 ES1 Evaluation Platform"
✔️ xitem.json: infra.revision = "1.2"
✔️ xitem.json: infra.description = "Versal VRK160 ES1 Evaluation Platform"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.2)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

1.3 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "vrk160"
✔️ board.xml: display_name = "VRK160 ES1 Evaluation Platform"
✔️ board.xml: <file_version> = 1.3
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xcvr1602-vsva2488-2MP-e-S-es1"
✔️ part0_pins.xml: 290 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 13 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "vrk160"
✔️ xitem.json: infra.display = "Versal VRK160 ES1 Evaluation Platform"
✔️ xitem.json: infra.revision = "1.3"
✔️ xitem.json: infra.description = "Versal VRK160 ES1 Evaluation Platform"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.3)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

1.0 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "vrk160_p"
✔️ board.xml: display_name = "VRK160 Evaluation Platform"
✔️ board.xml: <file_version> = 1.0
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xcvr1602-vsva2488-2MP-e-S"
✔️ part0_pins.xml: 290 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 13 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "vrk160"
✔️ xitem.json: infra.display = "Versal VRK160 Evaluation Platform"
✔️ xitem.json: infra.revision = "1.0"
✔️ xitem.json: infra.description = "Versal VRK160 Evaluation Platform"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

1.1 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "vrk165_es"
✔️ board.xml: display_name = "VRK165 ES1 Evaluation Platform"
✔️ board.xml: <file_version> = 1.1
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xcvr1652-vsva2488-2MP-e-S-es1"
✔️ part0_pins.xml: 290 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 13 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "vrk165"
✔️ xitem.json: infra.display = "Versal VRK165 ES1 Evaluation Platform"
✔️ xitem.json: infra.revision = "1.1"
✔️ xitem.json: infra.description = "Versal VRK165 ES1 Evaluation Platform"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

1.0 — ✅ Passed

Passed checks:

✔️ Required file present: board.xml
✔️ Required file present: part0_pins.xml
✔️ Required file present: preset.xml
✔️ board.xml: Well-formed XML
✔️ board.xml: Root element is
✔️ board.xml: vendor = "xilinx.com"
✔️ board.xml: name = "vrk165"
✔️ board.xml: display_name = "VRK165 Evaluation Platform"
✔️ board.xml: <file_version> = 1.0
✔️ board.xml: 1 compatible board revision(s) declared
✔️ board.xml: 1 FPGA component(s) declared
✔️ part0_pins.xml: Well-formed XML
✔️ part0_pins.xml: Root element is <part_info>
✔️ part0_pins.xml: part_name = "xcvr1652-vsva2488-2MP-e-S"
✔️ part0_pins.xml: 290 pin(s) defined
✔️ preset.xml: Well-formed XML
✔️ preset.xml: Root element is <ip_presets>
✔️ preset.xml: 13 preset entry/entries defined
✔️ xitem.json: Valid JSON
✔️ xitem.json: '_major' = 1
✔️ xitem.json: '_minor' = 0
✔️ xitem.json: infra.name = "vrk165"
✔️ xitem.json: infra.display = "Versal VRK165 Evaluation Platform"
✔️ xitem.json: infra.revision = "1.0"
✔️ xitem.json: infra.description = "Versal VRK165 Evaluation Platform"
✔️ xitem.json: infra.company = "xilinx.com"
✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

Generated by board_validator_basic.py — AMD/Xilinx Board Store CI

syncing files from GITE to GITHub

6d47e50

sabarinaxil requested a review from ADubeyAMD as a code owner August 11, 2026 05:52

xilinxgitops merged commit 6d47e50 into 2026.1.1 Aug 11, 2026
2 of 3 checks passed

sabarinaxil deleted the 2026.1.1_branching branch August 11, 2026 15:55

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CR-1000 : syncing files from GITE to GITHub - #845

CR-1000 : syncing files from GITE to GITHub#845
xilinxgitops merged 1 commit into
2026.1.1from
2026.1.1_branching

sabarinaxil commented Aug 11, 2026

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sabarinaxil commented Aug 11, 2026

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github-actions Bot commented Aug 11, 2026

🔍 Board Pre-Validation Report

✅ All pre-validation checks passed before merge

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