[DOC] Usb compound ip architecure doc - #14
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| The following diagram provides a detailed view of the USB compound device architecture, including its functional partitioning, internal connectivity, and main interfaces. | ||
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@ugomari-nxp : can we please break down the picture to a top level flow, followed by one click down of each stage. Currently its unreadable and doesn't present well
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| ### Interface Overview | ||
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| The JANUS top-level exposes interfaces for: |
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Need to remove all references to Janus since this is a public doc
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| - system clock, reset, and power-management coordination; | ||
| - connection to an external USB 2.0 PHY through UTMI or ULPI; | ||
| - independent AHB control of the embedded Hub, DEV0, and DEV1; |
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We should correct AHB references because we are going to have only AXI at the top of this block.
| category. Input groups are shown on the left side of the IP boundary, while | ||
| output and mixed-direction interface groups are shown on the right side. | ||
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| images/janus_top_level_interface.png |
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- some picture is missing and 2) we shld remove any janus references
| | USB PHY | UTMI and ULPI | Connects the shared USB PIE to an external USB 2.0 PHY. | | ||
| | Host control | Hub, DEV0, and DEV1 AHB register-control interfaces | Allows an external system master to configure and monitor the three USB functions. | | ||
| | External memory access | Hub Descriptor RAM and DEV0/DEV1 Endpoint RAM AHB interfaces | Allows an external system master to initialize, inspect, and update the USB memories. | | ||
| | Native memory | Hub Descriptor RAM and DEV0/DEV1 Endpoint RAM native interfaces | Connects JANUS to the three external RAM macros or memory models. | |
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It might be good to remove hub descriptor RAM references since we are making this update anyways, and spec can reflect the design even before design is done
| - AHB slave front-ends and AHB-to-memory adapters are reset by | ||
| `ahbs_resetn`. | ||
| - USB functional logic in the system-side clock domain is reset by | ||
| `hresetn`. |
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@clayton8 when we do the AXI and create the top level wrapper around this logic, we need a better name to standout than hreset; may be something like usb_reset_n or something of that nature that shows this is a whole module reset
| to remain active while clock shutdown or wake-up handling is still in | ||
| progress. | ||
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| #### Vendor-Specific UTMI Register Access |
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Can we define what vendor-specific UTMI register access means?
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| --- | ||
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| ## Host-Control AHB Interfaces |
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@clayton8 - this section needs an overhaul once we have AXI because AHB is not going to be publicly visible. If there are any specifical properties that SRAMs need to carry, like byte addressing we probably need to ensure that the AXI2AHB bridge supports that. Not sure if there is any other place where we support byte addressing. It might actually be easier and safer to make FW do RMW and do any byte stuff as a future enhancement if the AXI2AHB doesnt support it. Most last min bugs come from this type of logic.
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| The common behavior is: | ||
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| - byte-addressed AHB transfers; |
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@clayton8 here is the reference to the statement. We probably need to check if AXI2AHB supports it and need to fix this. I dont think we support byte addressing anywhere today and this might not be the time we want to start adding this support, this late
| The common behavior is: | ||
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| - byte-addressed AHB transfers; | ||
| - byte, half-word, and word access support; |
calebofearth
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USB Two-Port Compound Device IP architectural document