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[BSP][ra6w1]fix ra6w1 device bug #11722

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[BSP][ra6w1]fix ra6w1 device bug #11722

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45 changes: 34 additions & 11 deletions bsp/renesas/libraries/HAL_Drivers/drivers/drv_adc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -32,14 +32,14 @@

#elif defined(SOC_SERIES_R7SA6W1)

#define R_ADC_Open R_ADC_W_Open
#define R_ADC_ScanCfg R_ADC_W_ScanCfg
#define R_ADC_ScanStart R_ADC_W_ScanStart
#define R_ADC_Read32 R_ADC_W_Read32
#define R_ADC_Read R_ADC_W_Read
#define R_ADC_ScanStop R_ADC_W_ScanStop
#define R_ADC_Close R_ADC_W_Close

#define R_ADC_Open R_ADC_W_Open
#define R_ADC_ScanCfg R_ADC_W_ScanCfg
#define R_ADC_ScanStart R_ADC_W_ScanStart
#define R_ADC_Read32 R_ADC_W_Read32
#define R_ADC_Read R_ADC_W_Read
#define R_ADC_ScanStop R_ADC_W_ScanStop
#define R_ADC_Close R_ADC_W_Close
#define RA_ADC_FULL_SCALE_MV 1400
#endif

struct ra_adc_map ra_adc[] = {
Expand Down Expand Up @@ -113,18 +113,41 @@ static rt_err_t ra_get_adc_value(struct rt_adc_device *device, rt_int8_t channel
LOG_E("get adc value failed.\n");
return -RT_ERROR;
}
#if defined(SOC_SERIES_R7SA6W1)
/* R_ADC_W returns the 12-bit result left-aligned in a 16-bit FIFO field. */
*value >>= 4U;
#endif
return RT_EOK;
}

static rt_uint8_t ra_adc_get_resolution(struct rt_adc_device *device)
{
LOG_W("ra_adc_get_resolution is not supported.");
return 0;
struct ra_adc_map *adc;

RT_ASSERT(device != RT_NULL);
adc = (struct ra_adc_map *)device->parent.user_data;

switch (adc->g_cfg->resolution)
{
case ADC_RESOLUTION_12_BIT:
return 12;
case ADC_RESOLUTION_10_BIT:
return 10;
case ADC_RESOLUTION_7_BIT:
return 7;
case ADC_RESOLUTION_4_BIT:
return 4;
default:
return 0;
}
}
static rt_int16_t ra_adc_get_vref(struct rt_adc_device *device)
{
LOG_W("ra_adc_get_vref is not supported.");
#if defined(SOC_SERIES_R7SA6W1)
return RA_ADC_FULL_SCALE_MV;
#else
return 0;
#endif
}

static const struct rt_adc_ops ra_adc_ops = {
Expand Down
27 changes: 27 additions & 0 deletions bsp/renesas/ra6w1-ek/board/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -179,6 +179,19 @@ menu "Hardware Drivers Config"
bool "Enable I2C0 bus"
default n
if BSP_USING_HW_I2C0
choice BSP_USING_HW_I2C0_SPEED
prompt "I2C0 Baud Rate Settings"
default BSP_I2C0_RATE_FAST
config BSP_I2C0_RATE_STANDARD
bool "I2C_MASTER_RATE_STANDARD (100 kHz)"
config BSP_I2C0_RATE_FAST
bool "I2C_MASTER_RATE_FAST (400 kHz)"
config BSP_I2C0_RATE_FASTPLUS
bool "I2C_MASTER_RATE_FASTPLUS (1 MHz)"
config BSP_I2C0_RATE_HIGHSPEED
bool "I2C_MASTER_RATE_HIGHSPEED (3.4 MHz)"
endchoice

config BSP_I2C0_SCL_PIN
string "I2C0 SCL pin"
default "p004"
Expand All @@ -192,6 +205,20 @@ menu "Hardware Drivers Config"
bool "Enable I2C1 bus"
default n
if BSP_USING_HW_I2C1

choice BSP_USING_HW_I2C1_SPEED
prompt "I2C1 Baud Rate Settings"
default BSP_I2C1_RATE_FAST
config BSP_I2C1_RATE_STANDARD
bool "I2C_MASTER_RATE_STANDARD (100 kHz)"
config BSP_I2C1_RATE_FAST
bool "I2C_MASTER_RATE_FAST (400 kHz)"
config BSP_I2C1_RATE_FASTPLUS
bool "I2C_MASTER_RATE_FASTPLUS (1 MHz)"
config BSP_I2C1_RATE_HIGHSPEED
bool "I2C_MASTER_RATE_HIGHSPEED (3.4 MHz)"
endchoice

config BSP_I2C1_SCL_PIN
string "I2C1 SCL pin"
default "p006"
Expand Down
4 changes: 2 additions & 2 deletions bsp/renesas/ra6w1-ek/board/ports/drv_pwm_w.c
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
#include "drv_config.h"
#include "hal_data.h"

#if defined(BSP_USING_PWM) && \
#if defined(BSP_USING_PWM_W) && \
(defined(BSP_USING_PWM0) || defined(BSP_USING_PWM1) || \
defined(BSP_USING_PWM2) || defined(BSP_USING_PWM3) || \
defined(BSP_USING_PWM4) || defined(BSP_USING_PWM5) || \
Expand Down Expand Up @@ -217,4 +217,4 @@ static int rt_hw_pwm_w_init(void)
}
INIT_BOARD_EXPORT(rt_hw_pwm_w_init);

#endif /* BSP_USING_PWM */
#endif /* BSP_USING_PWM_W */
1 change: 1 addition & 0 deletions bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/board_cfg.h
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
/* generated configuration header file - do not edit */
#ifndef BOARD_CFG_H_
#define BOARD_CFG_H_
#define BSP_CFG_RTOS (3)
#include "../../../ra/board/rrq61xxx_evb/board.h"
#endif /* BOARD_CFG_H_ */
4 changes: 2 additions & 2 deletions bsp/renesas/ra6w1-ek/rafw_gen/bsp_clock_cfg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@
#define BSP_CFG_PLL_PERI_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* PLL_PERI Src: PLL */
#define BSP_CFG_PLL_PERI_DIV (BSP_CLOCKS_PLL_PERI_CLOCK_DIV_1_6) /* PLL_PERI Div /6 */
#define BSP_CFG_PERI_CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL_PERI) /* PERI_CLK Src: PLL */
#define BSP_CFG_I2C1CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_DIV1) /* I2C1 Div /1 */
#define BSP_CFG_I2C2CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_DIV1) /* I2C2 Div /1 */
#define BSP_CFG_I2C1CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_DIV2) /* I2C1 Div /2 */
#define BSP_CFG_I2C2CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_DIV2) /* I2C2 Div /2 */
#define BSP_CFG_WDOG_DIV (BSP_CLOCKS_WDOG_DIV_320) /* WDOG Div /320 */
#endif /* BSP_CLOCK_CFG_H_ */
66 changes: 58 additions & 8 deletions bsp/renesas/ra6w1-ek/rafw_gen/hal_data.c
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Original file line number Diff line number Diff line change
Expand Up @@ -422,6 +422,31 @@ RA6W1_TIM_INSTANCE_DEFINE(7, TIM_W_TIM8, VECTOR_NUMBER_TIMW7_IRQ)
#endif /* BSP_USING_TIM_W */

#ifdef BSP_USING_HW_I2C0

#if defined(BSP_I2C0_RATE_STANDARD)
/* 100 kHz: tLOW=4.77 us, tHIGH=5.22 us */
#define I2C0_MASTER_RATE I2C_MASTER_RATE_STANDARD
#define I2C0_MASTER_SCL_LCNT 187
#define I2C0_MASTER_SCL_HCNT 205

#elif defined(BSP_I2C0_RATE_FAST)
/* 400 kHz: tLOW=1.38 us, tHIGH=1.14 us */
#define I2C0_MASTER_RATE I2C_MASTER_RATE_FAST
#define I2C0_MASTER_SCL_LCNT 51
#define I2C0_MASTER_SCL_HCNT 41

#elif defined(BSP_I2C0_RATE_FASTPLUS)
/* 1 MHz: tLOW=580 ns, tHIGH=448 ns */
#define I2C0_MASTER_RATE I2C_MASTER_RATE_FASTPLUS
#define I2C0_MASTER_SCL_LCNT 19
#define I2C0_MASTER_SCL_HCNT 13

#elif defined(BSP_I2C0_RATE_HIGHSPEED)
#error "40 MHz I2C source cannot generate 3.4 MHz with the minimum HCNT/LCNT"
#else
#error "Select one BSP_I2C0_RATE_xxx option"
#endif

i2c_master_w_instance_ctrl_t g_i2c_master0_ctrl;

const i2c_master_w_extended_cfg_t g_i2c_master0_extend =
Expand All @@ -437,15 +462,15 @@ const i2c_master_w_extended_cfg_t g_i2c_master0_extend =
.gen_irq = FSP_INVALID_VECTOR,
#endif
.gen_ipl = 12,
/* Actual calculated bitrate: 399600. Actual calculated duty cycle: 50%. Frequency of the selected clock source: 80000000. */
.clock_settings.scl_lcnt = 100,
.clock_settings.scl_hcnt = 93,

.clock_settings.scl_lcnt = I2C0_MASTER_SCL_LCNT,
.clock_settings.scl_hcnt = I2C0_MASTER_SCL_HCNT,
};

const i2c_master_cfg_t g_i2c_master0_cfg =
{
.channel = 1 - I2C_MASTER_W_CHANNEL_OFFSET,
.rate = I2C_MASTER_RATE_FAST,
.rate = I2C0_MASTER_RATE,
.slave = 0x1D,
.addr_mode = I2C_MASTER_ADDR_MODE_7BIT,
.p_transfer_tx = NULL,
Expand Down Expand Up @@ -485,6 +510,31 @@ const i2c_master_instance_t g_i2c_master0 =
#endif

#ifdef BSP_USING_HW_I2C1

#if defined(BSP_I2C1_RATE_STANDARD)
/* 100 kHz: tLOW=4.77 us, tHIGH=5.22 us */
#define I2C1_MASTER_RATE I2C_MASTER_RATE_STANDARD
#define I2C1_MASTER_SCL_LCNT 187
#define I2C1_MASTER_SCL_HCNT 205

#elif defined(BSP_I2C1_RATE_FAST)
/* 400 kHz: tLOW=1.38 us, tHIGH=1.14 us */
#define I2C1_MASTER_RATE I2C_MASTER_RATE_FAST
#define I2C1_MASTER_SCL_LCNT 51
#define I2C1_MASTER_SCL_HCNT 41

#elif defined(BSP_I2C1_RATE_FASTPLUS)
/* 1 MHz: tLOW=580 ns, tHIGH=448 ns */
#define I2C1_MASTER_RATE I2C_MASTER_RATE_FASTPLUS
#define I2C1_MASTER_SCL_LCNT 19
#define I2C1_MASTER_SCL_HCNT 13

#elif defined(BSP_I2C1_RATE_HIGHSPEED)
#error "40 MHz I2C source cannot generate 3.4 MHz with the minimum HCNT/LCNT"
#else
#error "Select one BSP_I2C1_RATE_xxx option"
#endif

i2c_master_w_instance_ctrl_t g_i2c_master1_ctrl;

const i2c_master_w_extended_cfg_t g_i2c_master1_extend =
Expand All @@ -500,15 +550,15 @@ const i2c_master_w_extended_cfg_t g_i2c_master1_extend =
.gen_irq = FSP_INVALID_VECTOR,
#endif
.gen_ipl = 12,
/* Actual calculated bitrate: 399600. Actual calculated duty cycle: 50%. Frequency of the selected clock source: 80000000. */
.clock_settings.scl_lcnt = 100,
.clock_settings.scl_hcnt = 93,

.clock_settings.scl_lcnt = I2C1_MASTER_SCL_LCNT,
.clock_settings.scl_hcnt = I2C1_MASTER_SCL_HCNT,
};

const i2c_master_cfg_t g_i2c_master1_cfg =
{
.channel = 2 - I2C_MASTER_W_CHANNEL_OFFSET,
.rate = I2C_MASTER_RATE_FAST,
.rate = I2C1_MASTER_RATE,
.slave = 0x1D,
.addr_mode = I2C_MASTER_ADDR_MODE_7BIT,
.p_transfer_tx = NULL,
Expand Down
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