@@ -41,29 +41,23 @@ static void stm32_dma_enable_dmamux_clock(void)
4141/**
4242 * @brief Enable the clock of one DMA/BDMA controller and wait for the write to complete.
4343 * @param dma_rcc RCC enable bit of the DMA/BDMA controller.
44- * @param is_bdma RT_TRUE for BDMA clock enable, RT_FALSE for regular DMA.
44+ * @param type Type of the DMA/BDMA controller .
4545 */
46- static void stm32_dma_enable_clock (rt_uint32_t dma_rcc , rt_bool_t is_bdma )
46+ static void stm32_dma_enable_clock (rt_uint32_t dma_rcc ,
47+ stm32_dma_type type )
4748{
4849 rt_uint32_t tmpreg = 0x00U ;
4950
5051#if defined(BSP_USING_BDMA ) && (defined(SOC_SERIES_STM32H7 ) || defined(SOC_SERIES_STM32H7RS ))
51- if (is_bdma )
52+ if (type == STM32_DMA_TYPE_BDMA )
5253 {
53- if (dma_rcc == 0 )
54- {
55- LOG_E ("bdma enable clock failed, dma_rcc is 0" );
56- __HAL_RCC_BDMA_CLK_ENABLE ();
57- return ;
58- }
5954 SET_BIT (RCC -> AHB4ENR , dma_rcc );
6055 tmpreg = READ_BIT (RCC -> AHB4ENR , dma_rcc );
6156 UNUSED (tmpreg );
6257 return ;
6358 }
64- #endif /* BSP_USING_BDMA && (SOC_SERIES_STM32H7 || SOC_SERIES_STM32H7RS) */
6559
66- #if defined(STM32_DMA_USES_RCC_AHBENR )
60+ #elif defined(STM32_DMA_USES_RCC_AHBENR )
6761 SET_BIT (RCC -> AHBENR , dma_rcc );
6862 tmpreg = READ_BIT (RCC -> AHBENR , dma_rcc );
6963#elif defined(STM32_DMA_USES_RCC_MP_AHB2ENSETR )
@@ -283,21 +277,18 @@ static void stm32_dma_apply_config_common(DMA_HandleTypeDef *dma_handle,
283277 * @param dma_handle DMA handle owned by one peripheral driver.
284278 * @param common Common configuration fields shared by DMA and BDMA.
285279 * @param dma_config Optional DMA-specific configuration (NULL for BDMA).
286- * @param is_bdma RT_TRUE for BDMA, RT_FALSE for regular DMA.
287280 * @param log_tag Log tag for debug output ("drv.dma" or "drv.bdma").
288281 * @retval RT_EOK Initialization succeeded.
289282 * @retval -RT_ERROR HAL initialization failed.
290283 */
291284static rt_err_t stm32_dma_init_common (DMA_HandleTypeDef * dma_handle ,
292285 const struct stm32_dma_config_common * common ,
293286 const struct stm32_dma_config * dma_config ,
294- rt_bool_t is_bdma ,
295287 const char * log_tag )
296288{
297289 RT_ASSERT (dma_handle != RT_NULL );
298290 RT_ASSERT (common != RT_NULL );
299-
300- stm32_dma_enable_clock (common -> dma_rcc , is_bdma );
291+ stm32_dma_enable_clock (common -> dma_rcc , common -> type );
301292 stm32_dma_apply_config_common (dma_handle , common , dma_config );
302293
303294 LOG_D ("%s init, dma=%p, irq=%d" , log_tag , dma_handle -> Instance , common -> dma_irq );
@@ -324,7 +315,6 @@ static rt_err_t stm32_dma_init_common(DMA_HandleTypeDef *dma_handle,
324315 * @param dma_slot Address of the parent handle DMA slot, such as &huart->hdmarx.
325316 * @param common Common configuration fields shared by DMA and BDMA.
326317 * @param dma_config Optional DMA-specific configuration (NULL for BDMA).
327- * @param is_bdma RT_TRUE for BDMA, RT_FALSE for regular DMA.
328318 * @param log_tag Log tag for debug output ("drv.dma" or "drv.bdma").
329319 * @retval RT_EOK Initialization succeeded.
330320 * @retval -RT_ERROR HAL initialization failed.
@@ -334,12 +324,11 @@ static rt_err_t stm32_dma_setup_common(DMA_HandleTypeDef *dma_handle,
334324 DMA_HandleTypeDef * * dma_slot ,
335325 const struct stm32_dma_config_common * common ,
336326 const struct stm32_dma_config * dma_config ,
337- rt_bool_t is_bdma ,
338327 const char * log_tag )
339328{
340329 rt_err_t result ;
341330
342- result = stm32_dma_init_common (dma_handle , common , dma_config , is_bdma , log_tag );
331+ result = stm32_dma_init_common (dma_handle , common , dma_config , log_tag );
343332 if (result != RT_EOK )
344333 {
345334 return result ;
@@ -407,7 +396,7 @@ rt_err_t stm32_dma_init(DMA_HandleTypeDef *dma_handle,
407396 const struct stm32_dma_config * dma_config )
408397{
409398 RT_ASSERT (dma_config != RT_NULL );
410- return stm32_dma_init_common (dma_handle , & dma_config -> common , dma_config , RT_FALSE , "drv.dma" );
399+ return stm32_dma_init_common (dma_handle , & dma_config -> common , dma_config , "drv.dma" );
411400}
412401
413402/**
@@ -425,7 +414,7 @@ rt_err_t stm32_dma_setup(DMA_HandleTypeDef *dma_handle,
425414 const struct stm32_dma_config * dma_config )
426415{
427416 RT_ASSERT (dma_config != RT_NULL );
428- return stm32_dma_setup_common (dma_handle , parent_handle , dma_slot , & dma_config -> common , dma_config , RT_FALSE , "drv.dma" );
417+ return stm32_dma_setup_common (dma_handle , parent_handle , dma_slot , & dma_config -> common , dma_config , "drv.dma" );
429418}
430419
431420/**
@@ -457,7 +446,7 @@ rt_err_t stm32_bdma_init(DMA_HandleTypeDef *bdma_handle,
457446 const struct stm32_bdma_config * bdma_config )
458447{
459448 RT_ASSERT (bdma_config != RT_NULL );
460- return stm32_dma_init_common (bdma_handle , & bdma_config -> common , RT_NULL , RT_TRUE , LOG_TAG );
449+ return stm32_dma_init_common (bdma_handle , & bdma_config -> common , RT_NULL , LOG_TAG );
461450}
462451
463452/**
@@ -475,7 +464,7 @@ rt_err_t stm32_bdma_setup(DMA_HandleTypeDef *bdma_handle,
475464 const struct stm32_bdma_config * bdma_config )
476465{
477466 RT_ASSERT (bdma_config != RT_NULL );
478- return stm32_dma_setup_common (bdma_handle , parent_handle , dma_slot , & bdma_config -> common , RT_NULL , RT_TRUE , LOG_TAG );
467+ return stm32_dma_setup_common (bdma_handle , parent_handle , dma_slot , & bdma_config -> common , RT_NULL , LOG_TAG );
479468}
480469
481470/**
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