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[bsp][stm32] Add BDMA support for SPI and refactor DMA drivers
- Add BDMA support for SPI peripherals - Refactor and merge BDMA and DMA driver implementations - Update DMA and SPI configuration files for H7 series Co-Authored-By: Claude <noreply@anthropic.com>
1 parent 9d04b6b commit 44978e3

7 files changed

Lines changed: 819 additions & 363 deletions

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‎bsp/stm32/libraries/HAL_Drivers/drivers/SConscript‎

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Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ group = []
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src = []
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# DMA-capable BSPs are expected to enable HAL_DMA_MODULE_ENABLED in the
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# STM32 HAL configuration, so keep the common DMA helper in the build.
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src += ['drv_dma.c']
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path = [cwd]
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‎bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/dma_config.h‎

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Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
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/*
2-
* Copyright (c) 2006-2023, RT-Thread Development Team
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
@@ -8,6 +8,7 @@
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* 2019-01-02 zylx first version
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* 2019-01-08 SummerGift clean up the code
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* 2020-05-02 whj4674672 support stm32h7 dma1 and dma2
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* 2026-08-01 moment-NEW add BDMA support
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*/
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#ifndef __DMA_CONFIG_H__
@@ -21,136 +22,155 @@ extern "C" {
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2223
/* DMA1 stream0 */
2324
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
24-
#define UART2_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
25-
#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
26-
#define UART2_RX_DMA_INSTANCE DMA1_Stream0
27-
#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
28-
#define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn
25+
#define UART2_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
26+
#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART2_RX_DMA_INSTANCE DMA1_Stream0
28+
#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
29+
#define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn
2930
#endif
3031

3132
/* DMA1 stream1 */
3233
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
33-
#define UART2_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler
34-
#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
35-
#define UART2_TX_DMA_INSTANCE DMA1_Stream1
36-
#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX
37-
#define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn
34+
#define UART2_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler
35+
#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
36+
#define UART2_TX_DMA_INSTANCE DMA1_Stream1
37+
#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX
38+
#define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn
3839
#endif
3940

4041
/* DMA1 stream2 */
4142
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
42-
#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
43-
#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
44-
#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
45-
#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
43+
#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
44+
#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
45+
#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
46+
#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
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#endif
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4849
/* DMA1 stream3 */
4950
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
50-
#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
51-
#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
52-
#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
53-
#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
51+
#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
52+
#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
53+
#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
54+
#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
5455
#endif
5556

5657
/* DMA1 stream4 */
5758
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
58-
#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
59-
#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
60-
#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
61-
#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
59+
#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
60+
#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
61+
#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
62+
#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
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#endif
6364

6465

6566
/* DMA1 stream5 */
6667
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
67-
#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
68-
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
69-
#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
70-
#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
68+
#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
69+
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
70+
#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
71+
#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
7172
#endif
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7374
/* DMA1 stream6 */
7475

7576
/* DMA1 stream7 */
7677
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
77-
#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
78-
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
79-
#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
80-
#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
78+
#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
79+
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
80+
#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
81+
#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
8182
#endif
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8384
/* DMA2 stream0 */
8485
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
85-
#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
86-
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
87-
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
88-
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
86+
#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
87+
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
88+
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
89+
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
8990
#endif
9091

9192
/* DMA2 stream1 */
9293
#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
93-
#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
94-
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
95-
#define SPI4_TX_DMA_INSTANCE DMA2_Stream1
96-
#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
94+
#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
95+
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
96+
#define SPI4_TX_DMA_INSTANCE DMA2_Stream1
97+
#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
9798
#endif
9899

99100
/* DMA2 stream2 */
100101
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
101-
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
102-
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
103-
#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
104-
#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
102+
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
103+
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
104+
#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
105+
#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
105106
#endif
106107

107108
/* DMA2 stream3 */
108109
#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
109-
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
110-
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
111-
#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
112-
#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
110+
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
111+
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
112+
#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
113+
#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
113114
#endif
114115

115116
/* DMA2 stream4 */
116117
#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
117-
#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
118-
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
119-
#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
120-
#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
118+
#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
119+
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
120+
#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
121+
#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
121122
#endif
122123

123124
/* DMA2 stream5 */
124125
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
125-
#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
126-
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
127-
#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
128-
#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
126+
#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
127+
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
128+
#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
129+
#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
129130
#endif
130131

131132
/* DMA2 stream6 */
132133
#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
133-
#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
134-
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
135-
#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
136-
#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
134+
#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
135+
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
136+
#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
137+
#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
137138
#endif
138139

139140
/* DMA2 stream7 */
140141
#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
141-
#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
142-
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
143-
#define QSPI_DMA_INSTANCE DMA2_Stream7
142+
#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
143+
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
144+
#define QSPI_DMA_INSTANCE DMA2_Stream7
144145
#if defined(DMA_REQUEST_QUADSPI)
145-
#define QSPI_DMA_REQUEST DMA_REQUEST_QUADSPI
146+
#define QSPI_DMA_REQUEST DMA_REQUEST_QUADSPI
146147
#elif defined(DMA_REQUEST_QUADSPI1)
147-
#define QSPI_DMA_REQUEST DMA_REQUEST_QUADSPI1
148+
#define QSPI_DMA_REQUEST DMA_REQUEST_QUADSPI1
148149
#endif
149-
#define QSPI_DMA_IRQ DMA2_Stream7_IRQn
150+
#define QSPI_DMA_IRQ DMA2_Stream7_IRQn
150151
#endif
151152

153+
/*BDMA */
154+
#if defined(BSP_SPI6_TX_USING_BDMA) && !defined(SPI6_TX_BDMA_INSTANCE)
155+
#define SPI6_BDMA_TX_IRQHandler BDMA_Channel0_IRQHandler
156+
#define SPI6_TX_BDMA_INSTANCE BDMA_Channel0
157+
#define SPI6_TX_BDMA_RCC RCC_AHB4ENR_BDMAEN
158+
#define SPI6_TX_BDMA_REQUEST BDMA_REQUEST_SPI6_TX
159+
#define SPI6_TX_BDMA_IRQ BDMA_Channel0_IRQn
160+
#endif
161+
162+
#if defined(BSP_SPI6_RX_USING_BDMA) && !defined(SPI6_RX_BDMA_INSTANCE)
163+
#define SPI6_BDMA_RX_IRQHandler BDMA_Channel1_IRQHandler
164+
#define SPI6_RX_BDMA_INSTANCE BDMA_Channel1
165+
#define SPI6_RX_BDMA_RCC RCC_AHB4ENR_BDMAEN
166+
#define SPI6_RX_BDMA_REQUEST BDMA_REQUEST_SPI6_RX
167+
#define SPI6_RX_BDMA_IRQ BDMA_Channel1_IRQn
168+
#endif
169+
170+
152171
#ifdef __cplusplus
153172
}
154173
#endif
155174

156175
#endif /* __DMA_CONFIG_H__ */
176+

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