*** Pre-CBMEM romstage console overflowed, log truncated! *** lized. [DEBUG] TPM: Digest of `CBFS: fallback/romstage` to PCR 2 logged [DEBUG] BS: bootblock times (exec / console): total (unknown) / 0 ms [NOTE ] coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-2716-g9980b51 Thu Jan 01 00:00:00 UTC 1970 x86_32 romstage starting (log level: 6)... [DEBUG] Disabling Watchdog reboot... done. [DEBUG] SMBus controller enabled [DEBUG] Setting up static northbridge registers... done. [DEBUG] Started PEG11 link training. [DEBUG] Temporarily hiding PEG11. [DEBUG] Started PEG10 link training. [DEBUG] Temporarily hiding PEG10. [DEBUG] Initializing IGD... [DEBUG] Back from haswell_early_initialization() [DEBUG] CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i7-4810MQ CPU @ 2.80GHz [DEBUG] AES supported, TXT supported, VT supported [DEBUG] PCH type: QM87, device id: 8c4f, rev id 5 [ERROR] 0x00 failed to read [ERROR] 0x00 failed to read [DEBUG] Starting native platform initialisation [INFO ] Intel ME early init [INFO ] Intel ME firmware is ready [DEBUG] ME: Checking whether CPU was replaced... not replaced [DEBUG] HSIO lane owner: 0x05 [DEBUG] SATA port enables: 0x3f [DEBUG] warm_reset_usb3_ports: took 230 usecs [DEBUG] USB2 port 0 => mapped to OC pin 0 [DEBUG] USB2 port 1 => mapped to OC pin 0 [DEBUG] USB2 port 2 => mapped to OC pin 1 [DEBUG] USB2 port 3 => not mapped to OC pin [DEBUG] USB2 port 4 => not mapped to OC pin [DEBUG] USB2 port 5 => mapped to OC pin 2 [DEBUG] USB2 port 6 => mapped to OC pin 3 [DEBUG] USB2 port 7 => mapped to OC pin 3 [DEBUG] USB2 port 8 => mapped to OC pin 4 [DEBUG] USB2 port 9 => mapped to OC pin 4 [DEBUG] USB2 port 10 => mapped to OC pin 5 [DEBUG] USB2 port 11 => mapped to OC pin 5 [DEBUG] USB2 port 12 => mapped to OC pin 6 [DEBUG] USB2 port 13 => mapped to OC pin 6 [DEBUG] USB3 port 0 => mapped to OC pin 0 [DEBUG] USB3 port 1 => mapped to OC pin 0 [DEBUG] USB3 port 2 => not mapped to OC pin [DEBUG] USB3 port 3 => not mapped to OC pin [DEBUG] USB3 port 4 => mapped to OC pin 1 [DEBUG] USB3 port 5 => mapped to OC pin 1 [DEBUG] Retraining DMI at Gen2 speeds... [DEBUG] DMI: Running at Gen1 x4 [DEBUG] DMI: Running at Gen1 x4 [INFO ] DMI: Running at Gen2 x4 [DEBUG] Programming SA DMI VC/TC mappings... [DEBUG] Programming PCH DMI VC/TC mappings... [DEBUG] Waiting for PCH DMI VC negotiation... done! [DEBUG] Waiting for SA DMI VC negotiation... done! [DEBUG] FMAP: area RW_MRC_CACHE found @ 20000 (65536 bytes) [NOTE ] MRC: no data in 'RW_MRC_CACHE' [DEBUG] No MRC cache found. [DEBUG] FMAP: area COREBOOT found @ 30200 (12385792 bytes) [INFO ] CBFS: Found 'mrc.bin' @0xb6fdc0 size 0x36998 in mcache @0xff7c38d4 [INFO ] VB2:vb2_digest_init() 223640 bytes, hash algo 1, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: mrc.bin` to PCR 2 logged [DEBUG] Starting Memory Reference Code Initializing Policy Installing common PPI MRC: Starting... Initializing Memory MRC: Done. [DEBUG] MRC Version 1.8.0 Build 2 [DEBUG] memcfg DDR3 clock 1600 MHz [DEBUG] memcfg channel assignment: A: 0, B 1, C 2 [DEBUG] memcfg channel[0] config (00620020): [DEBUG] ECC inactive [DEBUG] enhanced interleave mode on [DEBUG] rank interleave on [DEBUG] DIMMA 8192 MB width x8 or x32 dual rank, selected [DEBUG] DIMMB 0 MB width x8 or x32 single rank [DEBUG] memcfg channel[1] config (00620020): [DEBUG] ECC inactive [DEBUG] enhanced interleave mode on [DEBUG] rank interleave on [DEBUG] DIMMA 8192 MB width x8 or x32 dual rank, selected [DEBUG] DIMMB 0 MB width x8 or x32 single rank [DEBUG] ME: Requested 0MB UMA [DEBUG] CBMEM: [DEBUG] IMD: root @ 0x7cfff000 254 entries. [DEBUG] IMD: root @ 0x7cffec00 62 entries. [DEBUG] External stage cache: [DEBUG] IMD: root @ 0x7d3ff000 254 entries. [DEBUG] IMD: root @ 0x7d3fec00 62 entries. [DEBUG] MRC data at 0xff7d0d9c 6246 bytes [DEBUG] FMAP: area RW_MRC_CACHE found @ 20000 (65536 bytes) [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. [DEBUG] flash size 0x2800000 bytes [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2800000 [ERROR] SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!! [NOTE ] MRC: no data in 'RW_MRC_CACHE' [DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update. [DEBUG] SF: Successfully written 2 bytes @ 0x20000 [DEBUG] SF: Successfully written 2 bytes @ 0x20002 [DEBUG] SF: Successfully written 20 bytes @ 0x20020 [DEBUG] SF: Successfully written 6246 bytes @ 0x20034 [DEBUG] MRC: updated 'RW_MRC_CACHE'. [DEBUG] Unhiding PEG10. [DEBUG] Unhiding PEG11. [DEBUG] SMM Memory Map [DEBUG] SMRAM : 0x7d000000 0x800000 [DEBUG] Subregion 0: 0x7d000000 0x300000 [DEBUG] Subregion 1: 0x7d300000 0x100000 [DEBUG] Subregion 2: 0x7d400000 0x400000 [DEBUG] Normal boot [INFO ] CBFS: Found 'fallback/postcar' @0x50880 size 0x7564 in mcache @0xff7c3864 [INFO ] VB2:vb2_digest_init() 30052 bytes, hash algo 1, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: fallback/postcar` to PCR 2 logged [DEBUG] Loading module at 0x7cfcb000 with entry 0x7cfcb031. filesize: 0x70c8 memsize: 0xd420 [DEBUG] Processing 279 relocs. Offset value of 0x7afcb000 [DEBUG] BS: romstage times (exec / console): total (unknown) / 492 ms [NOTE ] coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-2716-g9980b51 Thu Jan 01 00:00:00 UTC 1970 x86_32 postcar starting (log level: 6)... [DEBUG] Normal boot [DEBUG] FMAP: area COREBOOT found @ 30200 (12385792 bytes) [INFO ] CBFS: Found 'fallback/ramstage' @0x1dcc0 size 0x22dcf in mcache @0x7cfdd0ec [INFO ] VB2:vb2_digest_init() 142799 bytes, hash algo 1, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: fallback/ramstage` to PCR 2 logged [DEBUG] Loading module at 0x7ce72000 with entry 0x7ce72000. filesize: 0x44ca8 memsize: 0x157e30 [DEBUG] Processing 4392 relocs. Offset value of 0x78e72000 [DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms [NOTE ] coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-2716-g9980b51 Thu Jan 01 00:00:00 UTC 1970 x86_32 ramstage starting (log level: 6)... [DEBUG] Normal boot [INFO ] Enumerating buses... [DEBUG] Root Device scanning... [DEBUG] CPU_CLUSTER: 0 enabled [DEBUG] DOMAIN: 00000000 enabled [DEBUG] DOMAIN: 00000000 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 00 [DEBUG] PCI: 00:00:00.0 [8086/0c04] enabled [INFO ] PCI: Static device PCI: 00:00:01.0 not found, disabling it. [DEBUG] PCI: 00:00:01.1 [8086/0c05] enabled [DEBUG] PCI: 00:00:02.0 [8086/0416] enabled [DEBUG] PCI: 00:00:03.0 [8086/0c0c] enabled [DEBUG] PCI: 00:00:04.0 [8086/0c03] enabled [DEBUG] PCI: 00:00:14.0 [8086/8c31] enabled [DEBUG] PCI: 00:00:16.0 [8086/8c3a] enabled [DEBUG] PCI: 00:00:16.1: Disabling device [DEBUG] PCI: 00:00:16.2: Disabling device [DEBUG] PCI: 00:00:16.3: Disabling device [DEBUG] PCI: 00:00:19.0 [8086/153a] enabled [DEBUG] PCI: 00:00:1a.0 [8086/8c2d] enabled [DEBUG] PCI: 00:00:1b.0 [8086/8c20] enabled [DEBUG] PCIe Root Port 1 ASPM is disabled [DEBUG] PCI: 00:00:1c.0 [8086/8c10] enabled [DEBUG] PCIe Root Port 2 ASPM is disabled [DEBUG] PCI: 00:00:1c.1 [8086/8c12] enabled [DEBUG] PCI: 00:00:1c.2 [8086/8c14] disabled [DEBUG] PCI: 00:00:1c.3 [8086/8c16] disabled [DEBUG] Adjusted number of PCIe root ports to 5 as per strpfusecfg2 [DEBUG] PCI: 00:00:1c.2: Disabling device [DEBUG] PCI: 00:00:1c.3: Disabling device [DEBUG] PCI: 00:00:1c.4: Disabling device [DEBUG] PCI: 00:00:1c.4 [8086/8c18] disabled [DEBUG] PCI: 00:00:1d.0 [8086/8c26] enabled [DEBUG] PCI: 00:00:1f.0 [8086/8c4f] enabled [DEBUG] PCI: 00:00:1f.2 [8086/8c01] enabled [DEBUG] PCI: 00:00:1f.3 [8086/8c22] enabled [DEBUG] PCI: 00:00:1f.5: Disabling device [DEBUG] PCI: 00:00:1f.5 [8086/8c09] disabled [DEBUG] PCI: 00:00:1f.6: Disabling device [WARN ] PCI: Leftover static devices: [WARN ] PCI: 00:00:01.0 [WARN ] PCI: 00:00:16.1 [WARN ] PCI: 00:00:16.2 [WARN ] PCI: 00:00:16.3 [WARN ] PCI: 00:00:1c.5 [WARN ] PCI: 00:00:1c.6 [WARN ] PCI: 00:00:1c.7 [WARN ] PCI: 00:00:1f.6 [WARN ] PCI: Check your devicetree.cb. [DEBUG] PCI: 00:00:01.1 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 01 [INFO ] PCI: 00:00:01.1: Setting Max_Payload_Size to 128 for devices under this root port [DEBUG] scan_bus: bus PCI: 00:00:01.1 finished in 0 msecs [DEBUG] PCI: 00:00:1c.0 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 02 [DEBUG] PCI: 00:02:00.0 [10ec/5227] enabled [INFO ] Enabling Common Clock Configuration [INFO ] ASPM: Enabled L0s and L1 [INFO ] PCI: 00:02:00.0: Enabled LTR [INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port [DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 0 msecs [DEBUG] PCI: 00:00:1c.1 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 03 [DEBUG] PCI: 00:03:00.0 [8086/08b2] enabled [INFO ] Enabling Common Clock Configuration [INFO ] ASPM: Enabled L1 [INFO ] PCI: 00:03:00.0: Enabled LTR [INFO ] PCI: 00:00:1c.1: Setting Max_Payload_Size to 128 for devices under this root port [DEBUG] scan_bus: bus PCI: 00:00:1c.1 finished in 0 msecs [DEBUG] PCI: 00:00:1f.0 scanning... [INFO ] PMH7: ID 05 Revision 12 [DEBUG] PNP: 00ff.1 enabled [INFO ] H8: EC Firmware ID GLHT30WW-3.23, Version 3.01B [INFO ] H8: BDC detection not implemented. Assuming BDC installed [INFO ] H8: WWAN detection not implemented. Assuming WWAN installed [DEBUG] PNP: 00ff.2 enabled [INFO ] Found TPM 1.2 ST33ZP24 (0x0000) by ST Microelectronics (0x104a) [DEBUG] PNP: 0c31.0 enabled [DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 3 msecs [DEBUG] PCI: 00:00:1f.3 scanning... [DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs [DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 4 msecs [DEBUG] scan_bus: bus Root Device finished in 4 msecs [INFO ] done [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 4 / 0 ms [DEBUG] BM-LOCKDOWN: Enabling boot media protection scheme 'readonly' using CTRL... [DEBUG] flash size 0x2800000 bytes [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2800000 [ERROR] SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!! [INFO ] spi_flash_protect: FPR 0 is enabled for range 0x00000000-0x00bfffff [INFO ] BM-LOCKDOWN: Enabled bootmedia protection [DEBUG] found VGA at PCI: 00:00:02.0 [DEBUG] Setting up VGA for PCI: 00:00:02.0 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device [INFO ] Allocating resources... [INFO ] Reading resources... [DEBUG] mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff. [DEBUG] mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff. [DEBUG] mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff. [DEBUG] mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff. [DEBUG] mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff. [DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. [DEBUG] MC MAP: TOM: 0x400000000 [DEBUG] MC MAP: TOUUD: 0x480600000 [DEBUG] MC MAP: MESEG_BASE: 0x7ffff00000 [DEBUG] MC MAP: MESEG_LIMIT: 0xfffff [DEBUG] MC MAP: REMAP_BASE: 0x400000000 [DEBUG] MC MAP: REMAP_LIMIT: 0x4805fffff [DEBUG] MC MAP: TOLUD: 0x7fa00000 [DEBUG] MC MAP: BGSM: 0x7d800000 [DEBUG] MC MAP: BDSM: 0x7da00000 [DEBUG] MC MAP: TSEGMB: 0x7d000000 [DEBUG] MC MAP: GGC: 0x209 [DEBUG] MC MAP: DPR: 0x7d000000 [INFO ] Available memory above 4GB: 14342M [ERROR] PNP: 00ff.1 missing read_resources [ERROR] PNP: 00ff.2 missing read_resources [INFO ] Done reading resources. [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) === [DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 00:02:00.0 10 * [0x0 - 0xfff] mem [DEBUG] PCI: 00:00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done [DEBUG] PCI: 00:00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 00:00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 00:03:00.0 10 * [0x0 - 0x1fff] mem [DEBUG] PCI: 00:00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 00:00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) === [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 84 base 00001600 limit 0000167f io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 88 base 000015e0 limit 000015ef io (fixed) [DEBUG] avoid_fixed_resources: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed) [INFO ] DOMAIN: 00000000: Resource ranges: [INFO ] * Base: 1000, Size: 5e0, Tag: 100 [INFO ] * Base: 15f0, Size: 10, Tag: 100 [INFO ] * Base: 1680, Size: e980, Tag: 100 [DEBUG] PCI: 00:00:02.0 20 * [0xffc0 - 0xffff] limit: ffff io [DEBUG] PCI: 00:00:19.0 18 * [0xffa0 - 0xffbf] limit: ffbf io [DEBUG] PCI: 00:00:1f.2 20 * [0xff80 - 0xff9f] limit: ff9f io [DEBUG] PCI: 00:00:1f.2 10 * [0xff78 - 0xff7f] limit: ff7f io [DEBUG] PCI: 00:00:1f.2 18 * [0xff70 - 0xff77] limit: ff77 io [DEBUG] PCI: 00:00:1f.2 14 * [0xff6c - 0xff6f] limit: ff6f io [DEBUG] PCI: 00:00:1f.2 1c * [0xff68 - 0xff6b] limit: ff6b io [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done [DEBUG] DOMAIN: 00000000 mem: base: 7d000000 size: 0 align: 0 gran: 0 limit: efffffff [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 48 base fed10000 limit fed17fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 68 base fed18000 limit fed18fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 40 base fed19000 limit fed19fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 5420 base fed84000 limit fed84fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 5408 base fed80000 limit fed83fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base fed90000 limit fed90fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base fed91000 limit fed91fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base 00000000 limit 0009ffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base 000a0000 limit 000bffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base 000c0000 limit 000fffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base 00100000 limit 7cffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base 7d000000 limit 7d7fffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base 7d800000 limit 7f9fffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 100000000 limit 4805fffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 31fe base fec00000 limit ffffffff mem (fixed) [DEBUG] avoid_fixed_resources: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed) [INFO ] DOMAIN: 00000000: Resource ranges: [INFO ] * Base: 7fa00000, Size: 70600000, Tag: 200 [INFO ] * Base: 480600000, Size: 7b7fa00000, Tag: 200 [DEBUG] PCI: 00:00:02.0 18 * [0xe0000000 - 0xefffffff] limit: efffffff prefmem [DEBUG] PCI: 00:00:02.0 10 * [0xdfc00000 - 0xdfffffff] limit: dfffffff mem [DEBUG] PCI: 00:00:1c.0 20 * [0xdfb00000 - 0xdfbfffff] limit: dfbfffff mem [DEBUG] PCI: 00:00:1c.1 20 * [0xdfa00000 - 0xdfafffff] limit: dfafffff mem [DEBUG] PCI: 00:00:19.0 10 * [0xdf9e0000 - 0xdf9fffff] limit: df9fffff mem [DEBUG] PCI: 00:00:14.0 10 * [0xdf9d0000 - 0xdf9dffff] limit: df9dffff mem [DEBUG] PCI: 00:00:04.0 10 * [0xdf9c8000 - 0xdf9cffff] limit: df9cffff mem [DEBUG] PCI: 00:00:03.0 10 * [0xdf9c4000 - 0xdf9c7fff] limit: df9c7fff mem [DEBUG] PCI: 00:00:1b.0 10 * [0xdf9c0000 - 0xdf9c3fff] limit: df9c3fff mem [DEBUG] PCI: 00:00:19.0 14 * [0xdf9bf000 - 0xdf9bffff] limit: df9bffff mem [DEBUG] PCI: 00:00:1f.2 24 * [0xdf9be000 - 0xdf9be7ff] limit: df9be7ff mem [DEBUG] PCI: 00:00:1a.0 10 * [0xdf9bd000 - 0xdf9bd3ff] limit: df9bd3ff mem [DEBUG] PCI: 00:00:1d.0 10 * [0xdf9bc000 - 0xdf9bc3ff] limit: df9bc3ff mem [DEBUG] PCI: 00:00:1f.3 10 * [0xdf9bb000 - 0xdf9bb0ff] limit: df9bb0ff mem [DEBUG] PCI: 00:00:16.0 10 * [0xdf9ba000 - 0xdf9ba00f] limit: df9ba00f mem [DEBUG] DOMAIN: 00000000 mem: base: 7d000000 size: 0 align: 0 gran: 0 limit: efffffff done [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done [DEBUG] PCI: 00:02:00.0 10 * [0xdfb00000 - 0xdfb00fff] limit: dfb00fff mem [DEBUG] PCI: 00:03:00.0 10 * [0xdfa00000 - 0xdfa01fff] limit: dfa01fff mem [INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete === [DEBUG] PCI: 00:00:01.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio [DEBUG] PCI: 00:00:01.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem [DEBUG] PCI: 00:00:01.1 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bumem [DEBUG] PCI: 00:00:02.0 10 <- [0x00000000dfc00000 - 0x00000000dfffffff] size 0x00400000 gran 0x16 mem64 [DEBUG] PCI: 00:00:02.0 18 <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x1c prefmem64 [DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000ffc0 - 0x000000000000ffff] size 0x00000040 gran 0x06 io [DEBUG] PCI: 00:00:03.0 10 <- [0x00000000df9c4000 - 0x00000000df9c7fff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:00:04.0 10 <- [0x00000000df9c8000 - 0x00000000df9cffff] size 0x00008000 gran 0x0f mem64 [DEBUG] PCI: 00:00:14.0 10 <- [0x00000000df9d0000 - 0x00000000df9dffff] size 0x00010000 gran 0x10 mem64 [DEBUG] PCI: 00:00:16.0 10 <- [0x00000000df9ba000 - 0x00000000df9ba00f] size 0x00000010 gran 0x04 mem64 [DEBUG] PCI: 00:00:19.0 10 <- [0x00000000df9e0000 - 0x00000000df9fffff] size 0x00020000 gran 0x11 mem [DEBUG] PCI: 00:00:19.0 14 <- [0x00000000df9bf000 - 0x00000000df9bffff] size 0x00001000 gran 0x0c mem [DEBUG] PCI: 00:00:19.0 18 <- [0x000000000000ffa0 - 0x000000000000ffbf] size 0x00000020 gran 0x05 io [DEBUG] PCI: 00:00:1a.0 10 <- [0x00000000df9bd000 - 0x00000000df9bd3ff] size 0x00000400 gran 0x0a mem [DEBUG] PCI: 00:00:1b.0 10 <- [0x00000000df9c0000 - 0x00000000df9c3fff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio [DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem [DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000dfb00000 - 0x00000000dfbfffff] size 0x00100000 gran 0x14 seg 00 bumem [DEBUG] PCI: 00:02:00.0 10 <- [0x00000000dfb00000 - 0x00000000dfb00fff] size 0x00001000 gran 0x0c mem [DEBUG] PCI: 00:00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio [DEBUG] PCI: 00:00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem [DEBUG] PCI: 00:00:1c.1 20 <- [0x00000000dfa00000 - 0x00000000dfafffff] size 0x00100000 gran 0x14 seg 00 bumem [DEBUG] PCI: 00:03:00.0 10 <- [0x00000000dfa00000 - 0x00000000dfa01fff] size 0x00002000 gran 0x0d mem64 [DEBUG] PCI: 00:00:1d.0 10 <- [0x00000000df9bc000 - 0x00000000df9bc3ff] size 0x00000400 gran 0x0a mem [ERROR] PNP: 00ff.1 missing set_resources [ERROR] PNP: 00ff.2 missing set_resources [DEBUG] PCI: 00:00:1f.2 10 <- [0x000000000000ff78 - 0x000000000000ff7f] size 0x00000008 gran 0x03 io [DEBUG] PCI: 00:00:1f.2 14 <- [0x000000000000ff6c - 0x000000000000ff6f] size 0x00000004 gran 0x02 io [DEBUG] PCI: 00:00:1f.2 18 <- [0x000000000000ff70 - 0x000000000000ff77] size 0x00000008 gran 0x03 io [DEBUG] PCI: 00:00:1f.2 1c <- [0x000000000000ff68 - 0x000000000000ff6b] size 0x00000004 gran 0x02 io [DEBUG] PCI: 00:00:1f.2 20 <- [0x000000000000ff80 - 0x000000000000ff9f] size 0x00000020 gran 0x05 io [DEBUG] PCI: 00:00:1f.2 24 <- [0x00000000df9be000 - 0x00000000df9be7ff] size 0x00000800 gran 0x0b mem [DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000df9bb000 - 0x00000000df9bb0ff] size 0x00000100 gran 0x08 mem64 [INFO ] Done setting resources. [INFO ] Done allocating resources. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms [INFO ] Enabling resources... [DEBUG] PCI: 00:00:00.0 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:00.0 cmd <- 06 [DEBUG] PCI: 00:00:01.1 bridge ctrl <- 0013 [DEBUG] PCI: 00:00:01.1 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:01.1 cmd <- 00 [DEBUG] PCI: 00:00:02.0 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:02.0 cmd <- 03 [DEBUG] PCI: 00:00:03.0 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:03.0 cmd <- 02 [DEBUG] PCI: 00:00:04.0 cmd <- 02 [DEBUG] PCI: 00:00:14.0 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:14.0 cmd <- 102 [DEBUG] PCI: 00:00:16.0 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:16.0 cmd <- 02 [DEBUG] PCI: 00:00:19.0 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:19.0 cmd <- 103 [DEBUG] PCI: 00:00:1a.0 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:1a.0 cmd <- 106 [DEBUG] PCI: 00:00:1b.0 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:1b.0 cmd <- 102 [DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:00:1c.0 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:1c.0 cmd <- 06 [DEBUG] PCI: 00:00:1c.1 bridge ctrl <- 0013 [DEBUG] PCI: 00:00:1c.1 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:1c.1 cmd <- 06 [DEBUG] PCI: 00:00:1d.0 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:1d.0 cmd <- 106 [DEBUG] PCI: 00:00:1f.0 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:1f.0 cmd <- 107 [DEBUG] PCI: 00:00:1f.2 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:1f.2 cmd <- 103 [DEBUG] PCI: 00:00:1f.3 subsystem <- 17aa/220e [DEBUG] PCI: 00:00:1f.3 cmd <- 103 [DEBUG] PCI: 00:02:00.0 cmd <- 02 [DEBUG] PCI: 00:03:00.0 cmd <- 02 [INFO ] done. [INFO ] Initializing devices... [DEBUG] CPU_CLUSTER: 0 init [INFO ] LAPIC 0x0 in XAPIC mode. [DEBUG] MTRR: Physical address space: [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 [DEBUG] 0x00000000000c0000 - 0x000000007d7fffff size 0x7d740000 type 6 [DEBUG] 0x000000007d800000 - 0x00000000dfffffff size 0x62800000 type 0 [DEBUG] 0x00000000e0000000 - 0x00000000efffffff size 0x10000000 type 1 [DEBUG] 0x00000000f0000000 - 0x00000000ffffffff size 0x10000000 type 0 [DEBUG] 0x0000000100000000 - 0x00000004805fffff size 0x380600000 type 6 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits [DEBUG] MTRR: default type WB/UC MTRR counts: 6/7. [DEBUG] MTRR: WB selected as default type. [DEBUG] MTRR: 0 base 0x000000007d800000 mask 0x0000007fff800000 type 0 [DEBUG] MTRR: 1 base 0x000000007e000000 mask 0x0000007ffe000000 type 0 [DEBUG] MTRR: 2 base 0x0000000080000000 mask 0x0000007fc0000000 type 0 [DEBUG] MTRR: 3 base 0x00000000c0000000 mask 0x0000007fe0000000 type 0 [DEBUG] MTRR: 4 base 0x00000000e0000000 mask 0x0000007ff0000000 type 1 [DEBUG] MTRR: 5 base 0x00000000f0000000 mask 0x0000007ff0000000 type 0 [DEBUG] MTRR check [DEBUG] Fixed MTRRs : Enabled [DEBUG] Variable MTRRs: Enabled [DEBUG] Initializing VR config. [DEBUG] CPU has 4 cores, 8 threads enabled. [DEBUG] Setting up SMI for CPU [INFO ] Will perform SMM setup. [DEBUG] microcode: sig=0x306c3 pf=0x10 revision=0x28 [DEBUG] FMAP: area COREBOOT found @ 30200 (12385792 bytes) [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0xf800 in mcache @0x7cfdd02c [INFO ] VB2:vb2_digest_init() 63488 bytes, hash algo 1, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: cpu_microcode_blob.bin` to PCR 2 logged [INFO ] CPU: Intel(R) Core(TM) i7-4810MQ CPU @ 2.80GHz. [INFO ] LAPIC 0x0 in XAPIC mode. [DEBUG] CPU: APIC: 00 enabled [DEBUG] CPU: APIC: 01 enabled [DEBUG] CPU: APIC: 02 enabled [DEBUG] CPU: APIC: 03 enabled [DEBUG] CPU: APIC: 04 enabled [DEBUG] CPU: APIC: 05 enabled [DEBUG] CPU: APIC: 06 enabled [DEBUG] CPU: APIC: 07 enabled [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 [DEBUG] Processing 16 relocs. Offset value of 0x00030000 [DEBUG] Attempting to start 7 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [DEBUG] Waiting for SIPI to complete... [INFO ] LAPIC 0x1 in XAPIC mode. [DEBUG] done. [INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000028 [INFO ] LAPIC 0x2 in XAPIC mode. [INFO ] LAPIC 0x3 in XAPIC mode. [INFO ] AP: slot 2 apic_id 2, MCU rev: 0x00000028 [INFO ] AP: slot 3 apic_id 3, MCU rev: 0x00000028 [INFO ] LAPIC 0x4 in XAPIC mode. [INFO ] LAPIC 0x5 in XAPIC mode. [INFO ] AP: slot 4 apic_id 4, MCU rev: 0x00000028 [INFO ] AP: slot 5 apic_id 5, MCU rev: 0x00000028 [INFO ] LAPIC 0x6 in XAPIC mode. [INFO ] LAPIC 0x7 in XAPIC mode. [INFO ] AP: slot 6 apic_id 6, MCU rev: 0x00000028 [INFO ] AP: slot 7 apic_id 7, MCU rev: 0x00000028 [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0 [DEBUG] Processing 9 relocs. Offset value of 0x00038000 [DEBUG] smm_module_setup_stub: stack_top = 0x7d002000 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7ce9ec97 [DEBUG] Installing permanent SMM handler to 0x7d000000 [DEBUG] HANDLER [0x7d2ff000-0x7d2ffeef] [DEBUG] CPU 0 [DEBUG] ss0 [0x7d2fec00-0x7d2fefff] [DEBUG] stub0 [0x7d2f7000-0x7d2f719f] [DEBUG] CPU 1 [DEBUG] ss1 [0x7d2fe800-0x7d2febff] [DEBUG] stub1 [0x7d2f6c00-0x7d2f6d9f] [DEBUG] CPU 2 [DEBUG] ss2 [0x7d2fe400-0x7d2fe7ff] [DEBUG] stub2 [0x7d2f6800-0x7d2f699f] [DEBUG] CPU 3 [DEBUG] ss3 [0x7d2fe000-0x7d2fe3ff] [DEBUG] stub3 [0x7d2f6400-0x7d2f659f] [DEBUG] CPU 4 [DEBUG] ss4 [0x7d2fdc00-0x7d2fdfff] [DEBUG] stub4 [0x7d2f6000-0x7d2f619f] [DEBUG] CPU 5 [DEBUG] ss5 [0x7d2fd800-0x7d2fdbff] [DEBUG] stub5 [0x7d2f5c00-0x7d2f5d9f] [DEBUG] CPU 6 [DEBUG] ss6 [0x7d2fd400-0x7d2fd7ff] [DEBUG] stub6 [0x7d2f5800-0x7d2f599f] [DEBUG] CPU 7 [DEBUG] ss7 [0x7d2fd000-0x7d2fd3ff] [DEBUG] stub7 [0x7d2f5400-0x7d2f559f] [DEBUG] stacks [0x7d000000-0x7d001fff] [DEBUG] Loading module at 0x7d2ff000 with entry 0x7d2ff1d4. filesize: 0xed8 memsize: 0xef0 [DEBUG] Processing 53 relocs. Offset value of 0x7d2ff000 [DEBUG] Loading module at 0x7d2f7000 with entry 0x7d2f7000. filesize: 0x1a0 memsize: 0x1a0 [DEBUG] Processing 9 relocs. Offset value of 0x7d2f7000 [DEBUG] smm_module_setup_stub: stack_top = 0x7d002000 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000 [DEBUG] SMM Module: placing smm entry code at 7d2f6c00, cpu # 0x1 [DEBUG] SMM Module: placing smm entry code at 7d2f6800, cpu # 0x2 [DEBUG] SMM Module: placing smm entry code at 7d2f6400, cpu # 0x3 [DEBUG] SMM Module: placing smm entry code at 7d2f6000, cpu # 0x4 [DEBUG] SMM Module: placing smm entry code at 7d2f5c00, cpu # 0x5 [DEBUG] SMM Module: placing smm entry code at 7d2f5800, cpu # 0x6 [DEBUG] SMM Module: placing smm entry code at 7d2f5400, cpu # 0x7 [DEBUG] SMM Module: stub loaded at 7d2f7000. Will call 0x7d2ff1d4 [DEBUG] SMI_STS: MCSMI PM1 [DEBUG] TMROF smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7d2ef000, cpu = 0 [DEBUG] In relocation handler: CPU 0 [DEBUG] New SMBASE=0x7d2ef000 IEDBASE=0x7d400000 [DEBUG] Writing SMRR. base = 0x7d000006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7d2eec00, cpu = 1 [DEBUG] In relocation handler: CPU 1 [DEBUG] New SMBASE=0x7d2eec00 IEDBASE=0x7d400000 [DEBUG] Writing SMRR. base = 0x7d000006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7d2ed800, cpu = 6 [DEBUG] In relocation handler: CPU 6 [DEBUG] New SMBASE=0x7d2ed800 IEDBASE=0x7d400000 [DEBUG] Writing SMRR. base = 0x7d000006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7d2ee000, cpu = 4 [DEBUG] In relocation handler: CPU 4 [DEBUG] New SMBASE=0x7d2ee000 IEDBASE=0x7d400000 [DEBUG] Writing SMRR. base = 0x7d000006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7d2ee400, cpu = 3 [DEBUG] In relocation handler: CPU 3 [DEBUG] New SMBASE=0x7d2ee400 IEDBASE=0x7d400000 [DEBUG] Writing SMRR. base = 0x7d000006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7d2edc00, cpu = 5 [DEBUG] In relocation handler: CPU 5 [DEBUG] New SMBASE=0x7d2edc00 IEDBASE=0x7d400000 [DEBUG] Writing SMRR. base = 0x7d000006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7d2ed400, cpu = 7 [DEBUG] In relocation handler: CPU 7 [DEBUG] New SMBASE=0x7d2ed400 IEDBASE=0x7d400000 [DEBUG] Writing SMRR. base = 0x7d000006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7d2ee800, cpu = 2 [DEBUG] In relocation handler: CPU 2 [DEBUG] New SMBASE=0x7d2ee800 IEDBASE=0x7d400000 [DEBUG] Writing SMRR. base = 0x7d000006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL already locked [DEBUG] cpu: energy policy set to 6 [INFO ] Turbo is available but hidden [INFO ] Turbo is available and visible [INFO ] CPU #0 initialized [INFO ] Initializing CPU #1 [INFO ] Initializing CPU #4 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [INFO ] Initializing CPU #2 [INFO ] Initializing CPU #6 [INFO ] Initializing CPU #7 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [INFO ] Initializing CPU #5 [DEBUG] IA32_FEATURE_CONTROL already locked [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL already locked [DEBUG] IA32_FEATURE_CONTROL already locked [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled [DEBUG] cpu: energy policy set to 6 [INFO ] CPU #1 initialized [INFO ] Initializing CPU #3 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] IA32_FEATURE_CONTROL already locked [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled [DEBUG] cpu: energy policy set to 6 [DEBUG] cpu: energy policy set to 6 [INFO ] CPU #7 initialized [DEBUG] IA32_FEATURE_CONTROL already locked [INFO ] CPU #6 initialized [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL already locked [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled [DEBUG] cpu: energy policy set to 6 [DEBUG] IA32_FEATURE_CONTROL already locked [INFO ] CPU #4 initialized [DEBUG] cpu: energy policy set to 6 [INFO ] CPU #5 initialized [DEBUG] cpu: energy policy set to 6 [INFO ] CPU #2 initialized [DEBUG] cpu: energy policy set to 6 [INFO ] CPU #3 initialized [INFO ] bsp_do_flight_plan done after 3 msecs. [DEBUG] CPU: frequency set to 3800 [DEBUG] Enabling SMIs. [DEBUG] Locking SMM. [DEBUG] CPU_CLUSTER: 0 init finished in 57 msecs [DEBUG] PCI: 00:00:00.0 init [DEBUG] Disabling PEG12. [DEBUG] Disabling PEG10. [DEBUG] Disabling "device 7". [DEBUG] Set BIOS_RESET_CPL [DEBUG] CPU TDP: 47 Watts [DEBUG] PCI: 00:00:00.0 init finished in 1 msecs [DEBUG] PCI: 00:00:01.1 init [DEBUG] PCI: 00:00:01.1 init finished in 0 msecs [DEBUG] PCI: 00:00:02.0 init [INFO ] CBFS: Found 'vbt.bin' @0x4fd80 size 0x582 in mcache @0x7cfdd20c [INFO ] VB2:vb2_digest_init() 1410 bytes, hash algo 1, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: vbt.bin` to PCR 2 logged [INFO ] Found a VBT of 4608 bytes [INFO ] GMA: Found VBT in CBFS [INFO ] GMA: Found valid VBT in CBFS [DEBUG] GT Power Management Init [INFO ] GMA: Setting backlight PWM frequency to 135MHz / 128 / 4794 = 220Hz [INFO ] framebuffer_info: bytes_per_line: 6400, bits_per_pixel: 32 [INFO ] x_res x y_res: 1600 x 900, size: 5760000 at 0xe0000000 [DEBUG] GT Power Management Init (post VBIOS) [DEBUG] PCI: 00:00:02.0 init finished in 221 msecs [DEBUG] PCI: 00:00:03.0 init [DEBUG] Mini-HD: base = 0xdf9c4000 [DEBUG] HDA: No codec! [DEBUG] PCI: 00:00:03.0 init finished in 51 msecs [DEBUG] PCI: 00:00:04.0 init [DEBUG] PCI: 00:00:04.0 init finished in 0 msecs [DEBUG] PCI: 00:00:14.0 init [DEBUG] PCI: 00:00:14.0 init finished in 0 msecs [DEBUG] PCI: 00:00:16.0 init [CRIT ] intel_me_path: mbp is not ready! [NOTE ] ME: BIOS path: Error [ERROR] ME: MBP not ready [DEBUG] PCI: 00:00:16.0 init finished in 0 msecs [DEBUG] PCI: 00:00:19.0 init [DEBUG] PCI: 00:00:19.0 init finished in 0 msecs [DEBUG] PCI: 00:00:1a.0 init [DEBUG] EHCI: Setting up controller.. done. [DEBUG] PCI: 00:00:1a.0 init finished in 0 msecs [DEBUG] PCI: 00:00:1b.0 init [DEBUG] Azalia: base = 0xdf9c0000 [DEBUG] Azalia: codec_mask = 01 [DEBUG] azalia_audio: initializing codec #0... [DEBUG] azalia_audio: - vendor/device id: 0x10ec0292 [DEBUG] azalia_audio: - verb size: 128 [DEBUG] azalia_audio: - verb loaded [DEBUG] PCI: 00:00:1b.0 init finished in 7 msecs [DEBUG] PCI: 00:00:1c.0 init [DEBUG] Initializing PCH PCIe bridge. [DEBUG] PCI: 00:00:1c.0 init finished in 0 msecs [DEBUG] PCI: 00:00:1c.1 init [DEBUG] Initializing PCH PCIe bridge. [DEBUG] PCI: 00:00:1c.1 init finished in 0 msecs [DEBUG] PCI: 00:00:1d.0 init [DEBUG] EHCI: Setting up controller.. done. [DEBUG] PCI: 00:00:1d.0 init finished in 0 msecs [DEBUG] PCI: 00:00:1f.0 init [DEBUG] pch: lpc_init [DEBUG] IOAPIC: Initializing IOAPIC at fec00000 [DEBUG] IOAPIC: ID = 0x00 [DEBUG] IOAPIC: 24 interrupts [DEBUG] IOAPIC: Clearing IOAPIC at fec00000 [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 [INFO ] Set power off after power failure. [INFO ] NMI sources disabled. [DEBUG] LynxPoint H PM init [DEBUG] RTC: failed = 0x0 [DEBUG] RTC Init [DEBUG] apm_control: Disabling ACPI. [DEBUG] APMC done. [DEBUG] PCI: 00:00:1f.0 init finished in 0 msecs [DEBUG] PCI: 00:00:1f.2 init [DEBUG] SATA: Initializing... [DEBUG] SATA: Controller in AHCI mode. [DEBUG] ABAR: 0xdf9be000 [DEBUG] PCI: 00:00:1f.2 init finished in 0 msecs [DEBUG] PCI: 00:00:1f.3 init [DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs [DEBUG] PCI: 00:02:00.0 init [DEBUG] PCI: 00:02:00.0 init finished in 0 msecs [DEBUG] PCI: 00:03:00.0 init [DEBUG] PCI: 00:03:00.0 init finished in 0 msecs [DEBUG] PNP: 00ff.2 init [DEBUG] PNP: 00ff.2 init finished in 0 msecs [INFO ] Devices initialized [DEBUG] BS: BS_DEV_INIT run times (exec / console): 339 / 0 ms [DEBUG] TPM: Startup [DEBUG] TPM: command 0x99 returned 0x0 [DEBUG] TPM: Asserting physical presence [DEBUG] TPM: command 0x4000000a returned 0x0 [DEBUG] TPM: command 0x65 returned 0x0 [DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1 [DEBUG] TPM: Write digests cached in TPM log to PCR [DEBUG] TPM: Write digest for FMAP: FMAP into PCR 2 [DEBUG] TPM: command 0x14 returned 0x0 [DEBUG] TPM: Write digest for CBFS: bootblock into PCR 2 [DEBUG] TPM: command 0x14 returned 0x0 [DEBUG] TPM: Write digest for CBFS: fallback/romstage into PCR 2 [DEBUG] TPM: command 0x14 returned 0x0 [DEBUG] TPM: Write digest for CBFS: mrc.bin into PCR 2 [DEBUG] TPM: command 0x14 returned 0x0 [DEBUG] TPM: Write digest for CBFS: fallback/postcar into PCR 2 [DEBUG] TPM: command 0x14 returned 0x0 [DEBUG] TPM: Write digest for CBFS: fallback/ramstage into PCR 2 [DEBUG] TPM: command 0x14 returned 0x0 [DEBUG] TPM: Write digest for CBFS: cpu_microcode_blob.bin into PCR 2 [DEBUG] TPM: command 0x14 returned 0x0 [DEBUG] TPM: Write digest for CBFS: vbt.bin into PCR 2 [DEBUG] TPM: command 0x14 returned 0x0 [INFO ] TPM: setup succeeded [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 112 / 0 ms [INFO ] Finalize devices... [DEBUG] PCI: 00:00:00.0 final [DEBUG] PCI: 00:00:16.0 final [INFO ] ME: MBP cleared [DEBUG] PCI: 00:00:1b.0 final [DEBUG] PCI: 00:00:1f.0 final [INFO ] Devices finalized [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x4c580 size 0x3796 in mcache @0x7cfdd1e0 [INFO ] VB2:vb2_digest_init() 14230 bytes, hash algo 1, HW acceleration unsupported [DEBUG] TPM: Extending digest for `CBFS: fallback/dsdt.aml` into PCR 2 [DEBUG] TPM: command 0x14 returned 0x0 [DEBUG] TPM: Digest of `CBFS: fallback/dsdt.aml` to PCR 2 measured [WARN ] CBFS: 'fallback/slic' not found. [INFO ] ACPI: Writing ACPI tables at 7ce31000. [DEBUG] ACPI: * FACS [DEBUG] ACPI: * FACP [DEBUG] ACPI: added table 1/32, length now 44 [DEBUG] Found 1 CPU(s) with 8 core(s) each. [DEBUG] PSS: 2801MHz power 47000 control 0x2600 status 0x2600 [DEBUG] PSS: 2800MHz power 47000 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 38426 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 30571 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 23294 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 16615 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 10515 control 0x800 status 0x800 [DEBUG] PSS: 2801MHz power 47000 control 0x2600 status 0x2600 [DEBUG] PSS: 2800MHz power 47000 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 38426 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 30571 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 23294 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 16615 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 10515 control 0x800 status 0x800 [DEBUG] PSS: 2801MHz power 47000 control 0x2600 status 0x2600 [DEBUG] PSS: 2800MHz power 47000 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 38426 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 30571 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 23294 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 16615 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 10515 control 0x800 status 0x800 [DEBUG] PSS: 2801MHz power 47000 control 0x2600 status 0x2600 [DEBUG] PSS: 2800MHz power 47000 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 38426 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 30571 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 23294 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 16615 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 10515 control 0x800 status 0x800 [DEBUG] PSS: 2801MHz power 47000 control 0x2600 status 0x2600 [DEBUG] PSS: 2800MHz power 47000 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 38426 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 30571 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 23294 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 16615 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 10515 control 0x800 status 0x800 [DEBUG] PSS: 2801MHz power 47000 control 0x2600 status 0x2600 [DEBUG] PSS: 2800MHz power 47000 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 38426 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 30571 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 23294 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 16615 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 10515 control 0x800 status 0x800 [DEBUG] PSS: 2801MHz power 47000 control 0x2600 status 0x2600 [DEBUG] PSS: 2800MHz power 47000 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 38426 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 30571 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 23294 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 16615 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 10515 control 0x800 status 0x800 [DEBUG] PSS: 2801MHz power 47000 control 0x2600 status 0x2600 [DEBUG] PSS: 2800MHz power 47000 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 38426 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 30571 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 23294 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 16615 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 10515 control 0x800 status 0x800 [DEBUG] Generating ACPI PIRQ entries [INFO ] ACPI: * H8 [INFO ] H8: BDC detection not implemented. Assuming BDC installed [INFO ] H8: WWAN detection not implemented. Assuming WWAN installed [INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0 [DEBUG] ACPI: * SSDT [DEBUG] ACPI: added table 2/32, length now 52 [DEBUG] ACPI: * MCFG [DEBUG] ACPI: added table 3/32, length now 60 [DEBUG] TCPA log found at 0x7cfda000 [DEBUG] ACPI: * TCPA [DEBUG] ACPI: added table 4/32, length now 68 [DEBUG] IOAPIC: 24 interrupts [DEBUG] ACPI: * APIC [DEBUG] ACPI: added table 5/32, length now 76 [DEBUG] current = 7ce37250 [DEBUG] ACPI: * DMAR [DEBUG] ACPI: added table 6/32, length now 84 [DEBUG] ACPI: * HPET [DEBUG] ACPI: added table 7/32, length now 92 [DEBUG] current = 7ce37350 [INFO ] ACPI: done. [DEBUG] ACPI tables: 25424 bytes. [DEBUG] smbios_write_tables: 7ce29000 [DEBUG] BIOS version set to CONFIG_LOCALVERSION: 'Heads-v0.2.0-2716-g9980b51' [INFO ] Create SMBIOS type 16 [INFO ] Create SMBIOS type 17 [INFO ] Create SMBIOS type 20 [DEBUG] SMBIOS tables: 1104 bytes. [DEBUG] Writing table forward entry at 0x00000500 [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 32f9 [DEBUG] Writing coreboot table at 0x7ce55000 [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES [DEBUG] 1. 0000000000001000-000000000009ffff: RAM [DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED [DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES [DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED [DEBUG] 5. 0000000000100000-000000007ce28fff: RAM [DEBUG] 6. 000000007ce29000-000000007ce71fff: CONFIGURATION TABLES [DEBUG] 7. 000000007ce72000-000000007cfc9fff: RAMSTAGE [DEBUG] 8. 000000007cfca000-000000007cffffff: CONFIGURATION TABLES [DEBUG] 9. 000000007d000000-000000007f9fffff: RESERVED [DEBUG] 10. 00000000f0000000-00000000f3ffffff: RESERVED [DEBUG] 11. 00000000fed10000-00000000fed19fff: RESERVED [DEBUG] 12. 00000000fed40000-00000000fed44fff: RESERVED [DEBUG] 13. 00000000fed80000-00000000fed84fff: RESERVED [DEBUG] 14. 00000000fed90000-00000000fed91fff: RESERVED [DEBUG] 15. 0000000100000000-00000004805fffff: RAM [INFO ] Setting up bootsplash in 1600x900@32 [INFO ] CBFS: Found 'bootsplash.jpg' @0x41c40 size 0xa912 in mcache @0x7cfdd1b8 [INFO ] VB2:vb2_digest_init() 43282 bytes, hash algo 1, HW acceleration unsupported [DEBUG] TPM: Extending digest for `CBFS: bootsplash.jpg` into PCR 2 [DEBUG] TPM: command 0x14 returned 0x0 [DEBUG] TPM: Digest of `CBFS: bootsplash.jpg` to PCR 2 measured [DEBUG] Bootsplash image resolution: 1024x768 [INFO ] Bootsplash loaded [DEBUG] Wrote coreboot table at: 0x7ce55000, 0x43c bytes, checksum f2f3 [DEBUG] coreboot table: 1108 bytes. [DEBUG] IMD ROOT 0. 0x7cfff000 0x00001000 [DEBUG] IMD SMALL 1. 0x7cffe000 0x00001000 [DEBUG] CONSOLE 2. 0x7cfde000 0x00020000 [DEBUG] RO MCACHE 3. 0x7cfdd000 0x00000400 [DEBUG] TIME STAMP 4. 0x7cfdc000 0x00000910 [DEBUG] TCPA TCGLOG 5. 0x7cfda000 0x0000104c [DEBUG] MEM INFO 6. 0x7cfd9000 0x00000f48 [DEBUG] AFTER CAR 7. 0x7cfca000 0x0000f000 [DEBUG] RAMSTAGE 8. 0x7ce71000 0x00159000 [DEBUG] SMM BACKUP 9. 0x7ce61000 0x00010000 [DEBUG] IGD OPREGION10. 0x7ce5d000 0x00003130 [DEBUG] COREBOOT 11. 0x7ce55000 0x00008000 [DEBUG] ACPI 12. 0x7ce31000 0x00024000 [DEBUG] SMBIOS 13. 0x7ce29000 0x00008000 [DEBUG] IMD small region: [DEBUG] IMD ROOT 0. 0x7cffec00 0x00000400 [DEBUG] FMAP 1. 0x7cffeb20 0x000000e0 [DEBUG] ROMSTAGE 2. 0x7cffeb00 0x00000004 [DEBUG] ROMSTG STCK 3. 0x7cffea40 0x000000a8 [DEBUG] ACPI GNVS 4. 0x7cffe980 0x000000b0 [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 117 / 0 ms [INFO ] CBFS: Found 'fallback/payload' @0x57e40 size 0x74a62a in mcache @0x7cfdd2a8 [INFO ] VB2:vb2_digest_init() 7644714 bytes, hash algo 1, HW acceleration unsupported [DEBUG] TPM: Extending digest for `CBFS: fallback/payload` into PCR 2 [DEBUG] TPM: command 0x14 returned 0x0 [DEBUG] TPM: Digest of `CBFS: fallback/payload` to PCR 2 measured [DEBUG] Checking segment from ROM address 0xff48806c [DEBUG] Checking segment from ROM address 0xff488088 [DEBUG] Checking segment from ROM address 0xff4880a4 [DEBUG] Checking segment from ROM address 0xff4880c0 [DEBUG] Checking segment from ROM address 0xff4880dc [DEBUG] Checking segment from ROM address 0xff4880f8 [DEBUG] Loading segment from ROM address 0xff48806c [DEBUG] data (compression=0) [DEBUG] New segment dstaddr 0x00090000 memsize 0x1000 srcaddr 0xff488114 filesize 0x1000 [DEBUG] Loading Segment: addr: 0x00090000 memsz: 0x0000000000001000 filesz: 0x0000000000001000 [DEBUG] it's not compressed! [DEBUG] Loading segment from ROM address 0xff488088 [DEBUG] code (compression=0) [DEBUG] New segment dstaddr 0x01000000 memsize 0x2ad000 srcaddr 0xff489114 filesize 0x2ad000 [DEBUG] Loading Segment: addr: 0x01000000 memsz: 0x00000000002ad000 filesz: 0x00000000002ad000 [DEBUG] it's not compressed! [DEBUG] Loading segment from ROM address 0xff4880a4 [DEBUG] code (compression=0) [DEBUG] New segment dstaddr 0x00040000 memsize 0x171 srcaddr 0xff736114 filesize 0x171 [DEBUG] Loading Segment: addr: 0x00040000 memsz: 0x0000000000000171 filesz: 0x0000000000000171 [DEBUG] it's not compressed! [DEBUG] Loading segment from ROM address 0xff4880c0 [DEBUG] data (compression=0) [DEBUG] New segment dstaddr 0x00091000 memsize 0x11 srcaddr 0xff736285 filesize 0x11 [DEBUG] Loading Segment: addr: 0x00091000 memsz: 0x0000000000000011 filesz: 0x0000000000000011 [DEBUG] it's not compressed! [DEBUG] Loading segment from ROM address 0xff4880dc [DEBUG] data (compression=0) [DEBUG] New segment dstaddr 0x04000000 memsize 0x49c400 srcaddr 0xff736296 filesize 0x49c400 [DEBUG] Loading Segment: addr: 0x04000000 memsz: 0x000000000049c400 filesz: 0x000000000049c400 [DEBUG] it's not compressed! [DEBUG] Loading segment from ROM address 0xff4880f8 [DEBUG] Entry Point 0x00040000 [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 8328 / 0 ms [INFO ] coreboot TPM 1.2 measurements: [INFO ] PCR-2 3964868c3e32c845d2279b6276b5b980c79272f2 SHA1 [FMAP: FMAP] [INFO ] PCR-2 b248e4658d3caab4ac8579dd19ccb70fb6d8f6a5 SHA1 [CBFS: bootblock] [INFO ] PCR-2 774c0b9e145231f7c11da4f4a7518b92bd4320ab SHA1 [CBFS: fallback/romstage] [INFO ] PCR-2 eb2536a4e94c6d1cc6fe5dbd8952ae9b5acc535b SHA1 [CBFS: mrc.bin] [INFO ] PCR-2 328f192a644217083b393ec89c548ea7228a9a94 SHA1 [CBFS: fallback/postcar] [INFO ] PCR-2 8a81dd24ba88d91a8bd1600ec009660a17d012f4 SHA1 [CBFS: fallback/ramstage] [INFO ] PCR-2 2be3016289a8d4829c75438967d879bc19487704 SHA1 [CBFS: cpu_microcode_blob.bin] [INFO ] PCR-2 281d5cd4a67375632b491a7cf2ca1b2aece96d31 SHA1 [CBFS: vbt.bin] [INFO ] PCR-2 6f92816235b8659540cb3abe94e73eefa5f2b989 SHA1 [CBFS: fallback/dsdt.aml] [INFO ] PCR-2 ef3ad334fbfae32b516af1d0c4420adff24b49e1 SHA1 [CBFS: bootsplash.jpg] [INFO ] PCR-2 f11661e02c3555da725c8b3479f7ce5a481f4f65 SHA1 [CBFS: fallback/payload] [DEBUG] ICH-NM10-PCH: watchdog disabled [DEBUG] Jumping to boot code at 0x00040000(0x7ce55000)