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[Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march
RISC-V supports `-march`, `-mtune`, and `-mcpu`: `-march` provides the architecture extension information, `-mtune` provide the pipeline model, and `-mcpu` provides both. What's the priority among those options for now(w/o this patch)? Pipeline model: - Take from `-mtune` if present. - Take from `-mcpu` if present - Use the default pipeline model: `generic-rv32` or `generic-rv64` Architecture extension has quite complicated behavior now: - Take union from `-march` and `-mcpu` if both are present. - Take from `-march` if present. - Take from `-mcpu` if present. - Implied from `-mabi` if present. - Use the default architecture depending on the target triple We treat `-mcpu`/`-mtune` and `-mcpu`/`-march` differently, and it's kind of counterintuitive: -march is explicitly specified but ignored. This patch adjusts the priority between `-mcpu`/`-march`, letting it use architecture extension information from `-march` if it's present. So the priority of architecture extension information becomes: - Take from `-march` if present. - Take from `-mcpu` if present. - Implied from `-mabi` if present. - Use the default architecture depending on the target triple And this also match what we implement in RISC-V GCC too. Reviewed By: craig.topper, MaskRay Differential Revision: https://reviews.llvm.org/D140693
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Lines changed: 118 additions & 14 deletions

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‎clang/docs/ReleaseNotes.rst‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -803,6 +803,9 @@ RISC-V Support in Clang
803803
- ``sifive-7-rv32`` and ``sifive-7-rv64`` are no longer supported for ``-mcpu``.
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Use ``sifive-e76``, ``sifive-s76``, or ``sifive-u74`` instead.
805805
- Native detections via ``-mcpu=native`` and ``-mtune=native`` are supported.
806+
- Fix interaction of ``-mcpu`` and ``-march``, RISC-V backend will take the
807+
architecture extension union of ``-mcpu`` and ``-march`` before, and now will
808+
take architecture extensions from ``-march`` if both are given.
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X86 Support in Clang
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--------------------

‎clang/lib/Driver/ToolChains/Arch/RISCV.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,8 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
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}
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4545
(*ISAInfo)->toFeatures(
46-
Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); });
46+
Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
47+
/*AddAllExtensions=*/true);
4748
return true;
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}
4950

‎clang/test/Driver/riscv-cpus.c‎

Lines changed: 18 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,14 @@
99

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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-base | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-BASE %s
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// MCPU-SYNTACORE-SCR1-BASE: "-target-cpu" "syntacore-scr1-base"
12-
// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c" "-target-feature" "-64bit"
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// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c"
13+
// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "-64bit"
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// MCPU-SYNTACORE-SCR1-BASE: "-target-abi" "ilp32"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-max | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-MAX %s
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// MCPU-SYNTACORE-SCR1-MAX: "-target-cpu" "syntacore-scr1-max"
17-
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c" "-target-feature" "-64bit"
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// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c"
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// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "-64bit"
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// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
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// We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
@@ -80,42 +82,48 @@
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s
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// MCPU-ABI-SIFIVE-S21: "-nostdsysteminc" "-target-cpu" "sifive-s21"
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// MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a"
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// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c" "-target-feature" "+64bit"
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// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c"
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// MCPU-ABI-SIFIVE-S21: "-target-feature" "+64bit"
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// MCPU-ABI-SIFIVE-S21: "-target-abi" "lp64"
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// mcpu with mabi option
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
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// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
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// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
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// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
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// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c"
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// MCPU-ABI-SIFIVE-S51: "-target-feature" "+64bit"
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// MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
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// mcpu with default march
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s54 | FileCheck -check-prefix=MCPU-SIFIVE-S54 %s
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// MCPU-SIFIVE-S54: "-nostdsysteminc" "-target-cpu" "sifive-s54"
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// MCPU-SIFIVE-S54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
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// MCPU-SIFIVE-S54: "-target-feature" "+c" "-target-feature" "+64bit"
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// MCPU-SIFIVE-S54: "-target-feature" "+c"
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// MCPU-SIFIVE-S54: "-target-feature" "+64bit"
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// MCPU-SIFIVE-S54: "-target-abi" "lp64d"
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// mcpu with mabi option
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s76 | FileCheck -check-prefix=MCPU-SIFIVE-S76 %s
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// MCPU-SIFIVE-S76: "-nostdsysteminc" "-target-cpu" "sifive-s76"
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// MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
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// MCPU-SIFIVE-S76: "-target-feature" "+c" "-target-feature" "+64bit"
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// MCPU-SIFIVE-S76: "-target-feature" "+c"
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// MCPU-SIFIVE-S76: "-target-feature" "+64bit"
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// MCPU-SIFIVE-S76: "-target-abi" "lp64d"
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// mcpu with default march
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s
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// MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
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// MCPU-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
111-
// MCPU-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit"
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// MCPU-SIFIVE-U54: "-target-feature" "+c"
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// MCPU-SIFIVE-U54: "-target-feature" "+64bit"
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// MCPU-SIFIVE-U54: "-target-abi" "lp64d"
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// mcpu with mabi option
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U54 %s
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// MCPU-ABI-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
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// MCPU-ABI-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
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// MCPU-ABI-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit"
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// MCPU-ABI-SIFIVE-U54: "-target-feature" "+c"
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// MCPU-ABI-SIFIVE-U54: "-target-feature" "+64bit"
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// MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64"
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// mcpu with default march
@@ -129,7 +137,8 @@
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s
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// MCPU-ABI-SIFIVE-U74: "-nostdsysteminc" "-target-cpu" "sifive-u74"
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// MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
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// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c" "-target-feature" "+64bit"
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// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c"
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// MCPU-ABI-SIFIVE-U74: "-target-feature" "+64bit"
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// MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64"
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// march overwrite mcpu's default march

‎clang/test/Driver/riscv-default-features.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,10 @@
11
// RUN: %clang --target=riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
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// RUN: %clang --target=riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64
33

4-
// RV32: "target-features"="+32bit,+a,+c,+m,+relax,-save-restore"
5-
// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
4+
// RV32: "target-features"="+32bit,+a,+c,+m,+relax,
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// RV32-SAME: -save-restore
6+
// RV64: "target-features"="+64bit,+a,+c,+m,+relax,
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// RV64-SAME: -save-restore
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// Dummy function
810
int foo(void){

‎clang/test/Driver/riscv-march-mcpu-mtune.c‎

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@@ -0,0 +1,74 @@
1+
// Check the priority between -mcpu, -mtune and -march
2+
3+
// sifive-e76 is rv32imafc and sifive-e31 is rv32imac
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// -mcpu, -mtune and -march are not given, pipeline model and arch ext. use
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// default setting.
7+
// RUN: %clang --target=riscv32-elf -### -c %s 2>&1 \
8+
// RUN: | FileCheck -check-prefix=CHECK-DEFAULT %s
9+
// CHECK-DEFAULT: "-target-cpu" "generic-rv32"
10+
// CHECK-DEFAULT: "-target-feature" "+m" "-target-feature" "+a"
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// CHECK-DEFAULT: "-target-feature" "+c"
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// -mtune is given, pipeline model take from -mtune, arch ext. use
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// default setting.
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// RUN: %clang --target=riscv32 -mtune=sifive-e76 -### -c %s 2>&1 \
16+
// RUN: | FileCheck -check-prefix=MTUNE-E76 %s
17+
// MTUNE-E76: "-target-feature" "+m" "-target-feature" "+a"
18+
// MTUNE-E76: "-target-feature" "+c"
19+
// MTUNE-E76: "-target-feature" "-f"
20+
// MTUNE-E76: "-tune-cpu" "sifive-e76"
21+
22+
// -march is given, arch ext. take from -march, pipeline model use
23+
// default setting.
24+
// RUN: %clang --target=riscv32 -### -c %s -march=rv32imafdc 2>&1 \
25+
// RUN: | FileCheck -check-prefix=MARCH-RV32IMAFDC %s
26+
// MARCH-RV32IMAFDC: "-target-cpu" "generic-rv32"
27+
// MARCH-RV32IMAFDC: "-target-feature" "+m" "-target-feature" "+a"
28+
// MARCH-RV32IMAFDC: "-target-feature" "+f" "-target-feature" "+d"
29+
// MARCH-RV32IMAFDC: "-target-feature" "+c"
30+
31+
// -mcpu is given, pipeline model and arch ext. from -mcpu.
32+
// RUN: %clang --target=riscv32 -### -c %s -mcpu=sifive-e76 2>&1 \
33+
// RUN: | FileCheck -check-prefix=MCPU-E76 %s
34+
// MCPU-E76: "-target-cpu" "sifive-e76"
35+
// MCPU-E76: "-target-feature" "+m" "-target-feature" "+a"
36+
// MCPU-E76: "-target-feature" "+f" "-target-feature" "+c"
37+
38+
// -mcpu and -mtune are given, so pipeline model take from -mtune, and arch ext.
39+
// take from -mcpu since -march is not given.
40+
// RUN: %clang --target=riscv32 -### -c %s -mcpu=sifive-e76 -mtune=sifive-e31 2>&1 \
41+
// RUN: | FileCheck -check-prefix=MCPU-E76-MTUNE-E31 %s
42+
// MCPU-E76-MTUNE-E31: "-target-cpu" "sifive-e76"
43+
// MCPU-E76-MTUNE-E31: "-target-feature" "+m" "-target-feature" "+a"
44+
// MCPU-E76-MTUNE-E31: "-target-feature" "+f" "-target-feature" "+c"
45+
// MCPU-E76-MTUNE-E31: "-tune-cpu" "sifive-e31"
46+
47+
// RUN: %clang --target=riscv32 -### -c %s -mtune=sifive-e76 -mcpu=sifive-e31 2>&1 \
48+
// RUN: | FileCheck -check-prefix=MTUNE-E76-MCPU-E31 %s
49+
// MTUNE-E76-MCPU-E31: "-target-cpu" "sifive-e31"
50+
// MTUNE-E76-MCPU-E31: "-target-feature" "+m" "-target-feature" "+a"
51+
// MTUNE-E76-MCPU-E31: "-target-feature" "+c"
52+
// MTUNE-E76-MCPU-E31: "-target-feature" "-f"
53+
// MTUNE-E76-MCPU-E31: "-tune-cpu" "sifive-e76"
54+
55+
// -mcpu and -march are given, so pipeline model take from -mcpu since -mtune is
56+
// not given, and arch ext. take from -march.
57+
// RUN: %clang --target=riscv32 -### -c %s -mcpu=sifive-e31 -march=rv32ic 2>&1 \
58+
// RUN: | FileCheck -check-prefix=MCPU-E31-MARCH-RV32I %s
59+
// MCPU-E31-MARCH-RV32I: "-target-cpu" "sifive-e31"
60+
// MCPU-E31-MARCH-RV32I: "-target-feature" "+c"
61+
// MCPU-E31-MARCH-RV32I: "-target-feature" "-m"
62+
// MCPU-E31-MARCH-RV32I: "-target-feature" "-a"
63+
// MCPU-E31-MARCH-RV32I: "-target-feature" "-f"
64+
65+
// -mcpu, -march and -mtune are given, so pipeline model take from -mtune
66+
// and arch ext. take from -march, -mcpu is unused.
67+
// RUN: %clang --target=riscv32 -### -c %s -mcpu=sifive-e31 -mtune=sifive-e76 -march=rv32ic 2>&1 \
68+
// RUN: | FileCheck -check-prefix=MCPU-E31-MTUNE-E76-MARCH-RV32I %s
69+
// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-cpu" "sifive-e31"
70+
// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "+c"
71+
// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-m"
72+
// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-a"
73+
// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-f"
74+
// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-tune-cpu" "sifive-e76"

‎llvm/include/llvm/Support/RISCVISAInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,8 @@ class RISCVISAInfo {
5656

5757
/// Convert RISCV ISA info to a feature vector.
5858
void toFeatures(std::vector<StringRef> &Features,
59-
std::function<StringRef(const Twine &)> StrAlloc) const;
59+
llvm::function_ref<StringRef(const Twine &)> StrAlloc,
60+
bool AddAllExtensions) const;
6061

6162
const OrderedExtensionMap &getExtensions() const { return Exts; };
6263

‎llvm/lib/Support/RISCVISAInfo.cpp‎

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -331,7 +331,8 @@ bool RISCVISAInfo::compareExtension(const std::string &LHS,
331331

332332
void RISCVISAInfo::toFeatures(
333333
std::vector<StringRef> &Features,
334-
std::function<StringRef(const Twine &)> StrAlloc) const {
334+
llvm::function_ref<StringRef(const Twine &)> StrAlloc,
335+
bool AddAllExtensions) const {
335336
for (auto const &Ext : Exts) {
336337
StringRef ExtName = Ext.first;
337338

@@ -344,6 +345,19 @@ void RISCVISAInfo::toFeatures(
344345
Features.push_back(StrAlloc("+" + ExtName));
345346
}
346347
}
348+
if (AddAllExtensions) {
349+
for (const RISCVSupportedExtension &Ext : SupportedExtensions) {
350+
if (Exts.count(Ext.Name))
351+
continue;
352+
Features.push_back(StrAlloc(Twine("-") + Ext.Name));
353+
}
354+
355+
for (const RISCVSupportedExtension &Ext : SupportedExperimentalExtensions) {
356+
if (Exts.count(Ext.Name))
357+
continue;
358+
Features.push_back(StrAlloc(Twine("-experimental-") + Ext.Name));
359+
}
360+
}
347361
}
348362

349363
// Extensions may have a version number, and may be separated by

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