From 8bb30b803bdebadb3fa66e42813d480324186b9b Mon Sep 17 00:00:00 2001 From: Tiejun Zhou Date: Wed, 19 Apr 2023 08:39:58 +0000 Subject: [PATCH 1/3] Release ARMv7-A architecture ports --- ports_arch/ARMv7-A/README.md | 5 + .../common/example_build/sample_threadx.c | 369 ++ .../ARMv7-A/threadx/common/inc/tx_port.h | 331 ++ .../common/src/tx_thread_context_restore.S | 228 ++ .../common/src/tx_thread_context_save.S | 178 + .../src/tx_thread_fiq_context_restore.S | 229 ++ .../common/src/tx_thread_fiq_context_save.S | 184 + .../common/src/tx_thread_fiq_nesting_end.S | 110 + .../common/src/tx_thread_fiq_nesting_start.S | 102 + .../common/src/tx_thread_interrupt_control.S | 110 + .../common/src/tx_thread_interrupt_disable.S | 107 + .../common/src/tx_thread_interrupt_restore.S | 99 + .../common/src/tx_thread_irq_nesting_end.S | 109 + .../common/src/tx_thread_irq_nesting_start.S | 102 + .../threadx/common/src/tx_thread_schedule.S | 236 ++ .../common/src/tx_thread_stack_build.S | 171 + .../common/src/tx_thread_system_return.S | 168 + .../src/tx_thread_vectored_context_save.S | 171 + .../threadx/common/src/tx_timer_interrupt.S | 237 ++ .../ports/ac5/example_build/sample_threadx.c | 369 ++ .../example_build/tx_initialize_low_level.s | 370 ++ .../example_build/sample_threadx/.cproject | 176 + .../ac6/example_build/sample_threadx/.project | 27 + .../sample_threadx/sample_threadx.c | 369 ++ .../sample_threadx/sample_threadx.launch | 188 ++ .../sample_threadx/sample_threadx.scat | 44 + .../example_build/sample_threadx/startup.S | 397 +++ .../sample_threadx/tx_initialize_low_level.S | 299 ++ .../ports/ac6/example_build/tx/.cproject | 146 + .../ports/ac6/example_build/tx/.project | 48 + .../threadx/ports/gnu/example_build/crt0.S | 90 + .../threadx/ports/gnu/example_build/reset.S | 64 + .../ports/gnu/example_build/sample_threadx.c | 369 ++ .../ports/gnu/example_build/sample_threadx.ld | 239 ++ .../example_build/tx_initialize_low_level.S | 311 ++ .../ports/iar/example_build/azure_rtos.eww | 13 + .../ports/iar/example_build/cstartup.s | 156 + .../ports/iar/example_build/sample_threadx.c | 372 +++ .../iar/example_build/sample_threadx.ewd | 2974 +++++++++++++++++ .../iar/example_build/sample_threadx.ewp | 2130 ++++++++++++ .../iar/example_build/sample_threadx.icf | 49 + .../threadx/ports/iar/example_build/tx.ewp | 2763 +++++++++++++++ .../example_build/tx_initialize_low_level.s | 287 ++ ports_arch/ARMv7-A/update.ps1 | 183 + 44 files changed, 15679 insertions(+) create mode 100644 ports_arch/ARMv7-A/README.md create mode 100644 ports_arch/ARMv7-A/threadx/common/example_build/sample_threadx.c create mode 100644 ports_arch/ARMv7-A/threadx/common/inc/tx_port.h create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_restore.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_save.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_restore.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_save.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_end.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_start.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_control.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_disable.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_restore.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_end.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_start.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_stack_build.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_thread_vectored_context_save.S create mode 100644 ports_arch/ARMv7-A/threadx/common/src/tx_timer_interrupt.S create mode 100644 ports_arch/ARMv7-A/threadx/ports/ac5/example_build/sample_threadx.c create mode 100644 ports_arch/ARMv7-A/threadx/ports/ac5/example_build/tx_initialize_low_level.s create mode 100644 ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/.cproject create mode 100644 ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/.project create mode 100644 ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.c create mode 100644 ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.launch create mode 100644 ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.scat create mode 100644 ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/startup.S create mode 100644 ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/tx_initialize_low_level.S create mode 100644 ports_arch/ARMv7-A/threadx/ports/ac6/example_build/tx/.cproject create mode 100644 ports_arch/ARMv7-A/threadx/ports/ac6/example_build/tx/.project create mode 100644 ports_arch/ARMv7-A/threadx/ports/gnu/example_build/crt0.S create mode 100644 ports_arch/ARMv7-A/threadx/ports/gnu/example_build/reset.S create mode 100644 ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.c create mode 100644 ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.ld create mode 100644 ports_arch/ARMv7-A/threadx/ports/gnu/example_build/tx_initialize_low_level.S create mode 100644 ports_arch/ARMv7-A/threadx/ports/iar/example_build/azure_rtos.eww create mode 100644 ports_arch/ARMv7-A/threadx/ports/iar/example_build/cstartup.s create mode 100644 ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.c create mode 100644 ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.ewd create mode 100644 ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.ewp create mode 100644 ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.icf create mode 100644 ports_arch/ARMv7-A/threadx/ports/iar/example_build/tx.ewp create mode 100644 ports_arch/ARMv7-A/threadx/ports/iar/example_build/tx_initialize_low_level.s create mode 100644 ports_arch/ARMv7-A/update.ps1 diff --git a/ports_arch/ARMv7-A/README.md b/ports_arch/ARMv7-A/README.md new file mode 100644 index 000000000..3041f1964 --- /dev/null +++ b/ports_arch/ARMv7-A/README.md @@ -0,0 +1,5 @@ +# ARMv7-A architecture ports + +The ThreadX, ThreadX SMP, ThreadX Modules and ThreadX SMP Modules ports for ARMv7 share many files in common. +To make work more efficient these files are internally tracked only once and copied over to specific ports for users. + diff --git a/ports_arch/ARMv7-A/threadx/common/example_build/sample_threadx.c b/ports_arch/ARMv7-A/threadx/common/example_build/sample_threadx.c new file mode 100644 index 000000000..8c61de065 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_arch/ARMv7-A/threadx/common/inc/tx_port.h b/ports_arch/ARMv7-A/threadx/common/inc/tx_port.h new file mode 100644 index 000000000..6d5ee6087 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/inc/tx_port.h @@ -0,0 +1,331 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARMv7-A */ +/* 6.1.12 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define VFP extension for the ARMv7-A. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_restore.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_restore.S new file mode 100644 index 000000000..88c15c13f --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_restore.S @@ -0,0 +1,228 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 // Disable IRQ, SVC mode +IRQ_MODE = 0x92 // Disable IRQ, IRQ mode +#endif + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#else + CPSID i // Disable IRQ interrupts +#endif + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + + LDR r3, =_tx_thread_system_state // Pickup address of system state variable + LDR r2, [r3] // Pickup system state + SUB r2, r2, #1 // Decrement the counter + STR r2, [r3] // Store the counter + CMP r2, #0 // Was this the first interrupt? + BEQ __tx_thread_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 // Put SPSR back + LDMIA sp!, {r0-r3} // Recover r0-r3 + MOVS pc, lr // Return to point of interrupt + +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup actual current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_restore // Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR r2, [r3] // Pickup actual preempt disable flag + CMP r2, #0 // Is it set? + BNE __tx_thread_no_preempt_restore // Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR r2, [r3] // Pickup actual execute thread pointer + CMP r0, r2 // Is the same thread highest priority? + BNE __tx_thread_preempt_restore // No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Recover the saved context and return to the point of interrupt. */ + + /* Pickup the saved stack pointer. */ + + /* Recover the saved context and return to the point of interrupt. */ + LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 // Put SPSR back + LDMIA sp!, {r0-r3} // Recover r0-r3 + MOVS pc, lr // Return to point of interrupt + +__tx_thread_preempt_restore: + + LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + MOV r1, lr // Save lr (point of interrupt) + MOV r2, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r2 // Enter SVC mode + STR r1, [sp, #-4]! // Save point of interrupt + STMDB sp!, {r4-r12, lr} // Save upper half of registers + MOV r4, r3 // Save SPSR in r4 + MOV r2, #IRQ_MODE // Build IRQ mode CPSR + MSR CPSR_c, r2 // Enter IRQ mode + LDMIA sp!, {r0-r3} // Recover r0-r3 + MOV r5, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r5 // Enter SVC mode + STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save // No, skip VFP IRQ save + VMRS r2, FPSCR // Pickup the FPSCR + STR r2, [sp, #-4]! // Save FPSCR + VSTMDB sp!, {D16-D31} // Save D16-D31 + VSTMDB sp!, {D0-D15} // Save D0-D15 + +_tx_skip_irq_vfp_save: + +#endif + + MOV r3, #1 // Build interrupt stack type + STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + STR sp, [r0, #8] // Save stack pointer in thread control + // block + + /* Save the remaining time-slice and disable it. */ + LDR r3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR r2, [r3] // Pickup time-slice + CMP r2, #0 // Is it active? + BEQ __tx_thread_dont_save_ts // No, don't save it + STR r2, [r0, #24] // Save thread's time-slice + MOV r2, #0 // Clear value + STR r2, [r3] // Disable global time-slice flag + +__tx_thread_dont_save_ts: + + /* Clear the current task pointer. */ + MOV r0, #0 // NULL value + STR r0, [r1] // Clear current thread pointer + + /* Return to the scheduler. */ + B _tx_thread_schedule // Return to scheduler + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + MOV r0, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r0 // Enter SVC mode + B _tx_thread_schedule // Return to scheduler diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_save.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_save.S new file mode 100644 index 000000000..e24425bb5 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_save.S @@ -0,0 +1,178 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_irq_processing_return + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + + STMDB sp!, {r0-r3} // Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state // Pickup address of system state variable + LDR r2, [r3] // Pickup system state + CMP r2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} // Store other registers + + /* Return to the ISR. */ + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + B __tx_irq_processing_return // Continue IRQ processing + +__tx_thread_not_nested_save: + + /* Otherwise, not nested, check to see if a thread was running. */ + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3] // Store it back in the variable + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} // Store other registers + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + B __tx_irq_processing_return // Continue IRQ processing + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + ADD sp, sp, #16 // Recover saved registers + B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_restore.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_restore.S new file mode 100644 index 000000000..a0a834fbd --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,229 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + +SVC_MODE = 0xD3 // SVC mode +FIQ_MODE = 0xD1 // FIQ mode +MODE_MASK = 0x1F // Mode mask +THUMB_MASK = 0x20 // Thumb bit mask +IRQ_MODE_BITS = 0x12 // IRQ mode bits + + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_restore ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the fiq interrupt context when processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* FIQ ISR Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: + + /* Lockout interrupts. */ + + CPSID if // Disable IRQ and FIQ interrupts + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + LDR r3, =_tx_thread_system_state // Pickup address of system state variable + LDR r2, [r3] // Pickup system state + SUB r2, r2, #1 // Decrement the counter + STR r2, [r3] // Store the counter + CMP r2, #0 // Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 // Put SPSR back + LDMIA sp!, {r0-r3} // Recover r0-r3 + MOVS pc, lr // Return to point of interrupt + +__tx_thread_fiq_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + + LDR r1, [sp] // Pickup the saved SPSR + MOV r2, #MODE_MASK // Build mask to isolate the interrupted mode + AND r1, r1, r2 // Isolate mode bits + CMP r1, #IRQ_MODE_BITS // Was an interrupt taken in IRQ mode before we + // got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore // Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup actual current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore // Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR r2, [r3] // Pickup actual preempt disable flag + CMP r2, #0 // Is it set? + BNE __tx_thread_fiq_no_preempt_restore // Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR r2, [r3] // Pickup actual execute thread pointer + CMP r0, r2 // Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore // No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, lr} // Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 // Put SPSR back + LDMIA sp!, {r0-r3} // Recover r0-r3 + MOVS pc, lr // Return to point of interrupt + +__tx_thread_fiq_preempt_restore: + + LDMIA sp!, {r3, lr} // Recover temporarily saved registers + MOV r1, lr // Save lr (point of interrupt) + MOV r2, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r2 // Enter SVC mode + STR r1, [sp, #-4]! // Save point of interrupt + STMDB sp!, {r4-r12, lr} // Save upper half of registers + MOV r4, r3 // Save SPSR in r4 + MOV r2, #FIQ_MODE // Build FIQ mode CPSR + MSR CPSR_c, r2 // Reenter FIQ mode + LDMIA sp!, {r0-r3} // Recover r0-r3 + MOV r5, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r5 // Enter SVC mode + STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save // No, skip VFP IRQ save + VMRS r2, FPSCR // Pickup the FPSCR + STR r2, [sp, #-4]! // Save FPSCR + VSTMDB sp!, {D16-D31} // Save D16-D31 + VSTMDB sp!, {D0-D15} // Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 // Build interrupt stack type + STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + STR sp, [r0, #8] // Save stack pointer in thread control + // block */ + LDR r3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR r2, [r3] // Pickup time-slice + CMP r2, #0 // Is it active? + BEQ __tx_thread_fiq_dont_save_ts // No, don't save it + + STR r2, [r0, #24] // Save thread's time-slice + MOV r2, #0 // Clear value + STR r2, [r3] // Disable global time-slice flag + +__tx_thread_fiq_dont_save_ts: + + /* Clear the current task pointer. */ + + MOV r0, #0 // NULL value + STR r0, [r1] // Clear current thread pointer + + /* Return to the scheduler. */ + + B _tx_thread_schedule // Return to scheduler + +__tx_thread_fiq_idle_system_restore: + + /* Just return back to the scheduler! */ + + ADD sp, sp, #24 // Recover FIQ stack space + MOV r3, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r3 // Lockout interrupts + B _tx_thread_schedule // Return to scheduler + diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_save.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_save.S new file mode 100644 index 000000000..57b8d73b2 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_save.S @@ -0,0 +1,184 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return + .global _tx_execution_isr_enter + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_save ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + + STMDB sp!, {r0-r3} // Save some working registers + LDR r3, =_tx_thread_system_state // Pickup address of system state variable + LDR r2, [r3] // Pickup system state + CMP r2, #0 // Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} // Store other registers + + /* Return to the ISR. */ + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + B __tx_fiq_processing_return // Continue FIQ processing +// +__tx_thread_fiq_not_nested_save: + + /* Otherwise, not nested, check to see if a thread was running. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3] // Store it back in the variable + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_fiq_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r2, lr} // Store other registers, Note that we don't + // need to save sl and ip since FIQ has + // copies of these registers. Nested + // interrupt processing does need to save + // these registers. + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + B __tx_fiq_processing_return // Continue FIQ processing + +__tx_thread_fiq_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + /* Not much to do here, save the current SPSR and LR for possible + use in IRQ interrupted in idle system conditions, and return to + FIQ interrupt processing. */ + + MRS r0, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r0, lr} // Store other registers that will get used + // or stripped off the stack in context + // restore + B __tx_fiq_processing_return // Continue FIQ processing diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_end.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 000000000..f14a39eb4 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 // Disable IRQ interrupts +#endif +MODE_MASK = 0x1F // Mode mask +FIQ_MODE_BITS = 0x11 // FIQ mode bits + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_end ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +/* processing from system mode back to FIQ mode prior to the ISR */ +/* calling _tx_thread_fiq_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.s). */ +/* */ +/* This function returns with FIQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr // Save ISR return address + MRS r0, CPSR // Pickup the CPSR + ORR r0, r0, #DISABLE_INTS // Build disable interrupt value + MSR CPSR_c, r0 // Disable interrupts + LDMIA sp!, {r1, lr} // Pickup saved lr (and r1 throw-away for + // 8-byte alignment logic) + BIC r0, r0, #MODE_MASK // Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR + MSR CPSR_c, r0 // Reenter IRQ mode + +#ifdef __THUMB_INTERWORK + BX r3 // Return to caller +#else + MOV pc, r3 // Return to caller +#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_start.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 000000000..b4d61ac8f --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + +FIQ_DISABLE = 0x40 // FIQ disable bit +MODE_MASK = 0x1F // Mode mask +SYS_MODE_BITS = 0x1F // System mode bits + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_start ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +/* processing to the system mode so nested FIQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.s). */ +/* */ +/* This function returns with FIQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr // Save ISR return address + MRS r0, CPSR // Pickup the CPSR + BIC r0, r0, #MODE_MASK // Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS // Build system mode CPSR + MSR CPSR_c, r0 // Enter system mode + STMDB sp!, {r1, lr} // Push the system mode lr on the system mode stack + // and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR + MSR CPSR_c, r0 // Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 // Return to caller +#else + MOV pc, r3 // Return to caller +#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_control.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_control.S new file mode 100644 index 000000000..8a3b4edef --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_control.S @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + +INT_MASK = 0x03F + + +/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS r3, CPSR // Pickup current CPSR + MOV r2, #INT_MASK // Build interrupt mask + AND r1, r3, r2 // Clear interrupt lockout bits + ORR r1, r1, r0 // Or-in new interrupt lockout bits + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r1 // Setup new CPSR + BIC r0, r3, r2 // Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_disable.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_disable.S new file mode 100644 index 000000000..f4b9e31b9 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_disable.S @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + +/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS r0, CPSR // Pickup current CPSR + + /* Mask interrupts. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ +#else + CPSID i // Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_restore.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_restore.S new file mode 100644 index 000000000..9bd4cb300 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_restore.S @@ -0,0 +1,99 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + +/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r0 // Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_end.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_end.S new file mode 100644 index 000000000..8c2f4b92c --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 // Disable IRQ interrupts +#endif +MODE_MASK = 0x1F // Mode mask +IRQ_MODE_BITS = 0x12 // IRQ mode bits + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_end ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +/* processing from system mode back to IRQ mode prior to the ISR */ +/* calling _tx_thread_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.s). */ +/* */ +/* This function returns with IRQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr // Save ISR return address + MRS r0, CPSR // Pickup the CPSR + ORR r0, r0, #DISABLE_INTS // Build disable interrupt value + MSR CPSR_c, r0 // Disable interrupts + LDMIA sp!, {r1, lr} // Pickup saved lr (and r1 throw-away for + // 8-byte alignment logic) + BIC r0, r0, #MODE_MASK // Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR + MSR CPSR_c, r0 // Reenter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 // Return to caller +#else + MOV pc, r3 // Return to caller +#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_start.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_start.S new file mode 100644 index 000000000..35727b89f --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + +IRQ_DISABLE = 0x80 // IRQ disable bit +MODE_MASK = 0x1F // Mode mask +SYS_MODE_BITS = 0x1F // System mode bits + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_start ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_context_save has been called and switches the IRQ */ +/* processing to the system mode so nested IRQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.s). */ +/* */ +/* This function returns with IRQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr // Save ISR return address + MRS r0, CPSR // Pickup the CPSR + BIC r0, r0, #MODE_MASK // Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS // Build system mode CPSR + MSR CPSR_c, r0 // Enter system mode + STMDB sp!, {r1, lr} // Push the system mode lr on the system mode stack + // and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR + MSR CPSR_c, r0 // Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 // Return to caller +#else + MOV pc, r3 // Return to caller +#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S new file mode 100644 index 000000000..6af94e945 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S @@ -0,0 +1,236 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + + +/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_thread_schedule // Call _tx_thread_schedule function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: + + /* Enable interrupts. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if // Enable IRQ and FIQ interrupts +#else + CPSIE i // Enable IRQ interrupts +#endif + + /* Wait for a thread to execute. */ + LDR r1, =_tx_thread_execute_ptr // Address of thread execute ptr + +__tx_thread_schedule_loop: + + LDR r0, [r1] // Pickup next thread to execute + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_schedule_loop // If so, keep looking for a thread + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#else + CPSID i // Disable IRQ interrupts +#endif + + /* Setup the current thread pointer. */ + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread + STR r0, [r1] // Setup current thread pointer + + /* Increment the run count for this thread. */ + + LDR r2, [r0, #4] // Pickup run counter + LDR r3, [r0, #24] // Pickup time-slice for this thread + ADD r2, r2, #1 // Increment thread run-counter + STR r2, [r0, #4] // Store the new run counter + + /* Setup time-slice, if present. */ + + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice + // variable + LDR sp, [r0, #8] // Switch stack pointers + STR r3, [r2] // Setup time-slice + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV r5, r0 // Save r0 + BL _tx_execution_thread_enter // Call the thread execution enter function + MOV r0, r5 // Restore r0 +#endif + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + CMP r4, #0 // Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 // Setup SPSR for return +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] // Pickup the VFP enabled flag + CMP r1, #0 // Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} // Recover D0-D15 + VLDMIA sp!, {D16-D31} // Recover D16-D31 + LDR r4, [sp], #4 // Pickup FPSCR + VMSR FPSCR, r4 // Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ // Return to point of thread interrupt + +_tx_solicited_return: + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] // Pickup the VFP enabled flag + CMP r1, #0 // Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore // No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} // Recover D8-D15 + VLDMIA sp!, {D16-D31} // Recover D16-D31 + LDR r4, [sp], #4 // Pickup FPSCR + VMSR FPSCR, r4 // Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 // Recover CPSR + LDMIA sp!, {r4-r11, lr} // Return to thread synchronously +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif + +#ifdef TX_ENABLE_VFP_SUPPORT + + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable,function +tx_thread_vfp_enable: + MRS r2, CPSR // Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Enable IRQ and FIQ interrupts +#else + CPSID i // Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup current thread pointer + CMP r1, #0 // Check for NULL thread pointer + BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable + MOV r0, #1 // Build enable value + STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 // Recover CPSR + BX LR // Return to caller + + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable,function +tx_thread_vfp_disable: + MRS r2, CPSR // Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Enable IRQ and FIQ interrupts +#else + CPSID i // Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup current thread pointer + CMP r1, #0 // Check for NULL thread pointer + BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable + MOV r0, #0 // Build disable value + STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 // Recover CPSR + BX LR // Return to caller + +#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_stack_build.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_stack_build.S new file mode 100644 index 000000000..7aa7c0877 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_stack_build.S @@ -0,0 +1,171 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + + .arm + +SVC_MODE = 0x13 // SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +#endif + + +/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_thread_stack_build // Call _tx_thread_stack_build function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the ARMv7-A should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + CPSR Initial value for CPSR + a1 (r0) Initial value for a1 + a2 (r1) Initial value for a2 + a3 (r2) Initial value for a3 + a4 (r3) Initial value for a4 + v1 (r4) Initial value for v1 + v2 (r5) Initial value for v2 + v3 (r6) Initial value for v3 + v4 (r7) Initial value for v4 + v5 (r8) Initial value for v5 + sb (r9) Initial value for sb + sl (r10) Initial value for sl + fp (r11) Initial value for fp + ip (r12) Initial value for ip + lr (r14) Initial value for lr + pc (r15) Initial value for + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #7 // Ensure 8-byte alignment + SUB r2, r2, #76 // Allocate space for the stack frame + + /* Actually build the stack frame. */ + + MOV r3, #1 // Build interrupt stack type + STR r3, [r2, #0] // Store stack type + MOV r3, #0 // Build initial register value + STR r3, [r2, #8] // Store initial r0 + STR r3, [r2, #12] // Store initial r1 + STR r3, [r2, #16] // Store initial r2 + STR r3, [r2, #20] // Store initial r3 + STR r3, [r2, #24] // Store initial r4 + STR r3, [r2, #28] // Store initial r5 + STR r3, [r2, #32] // Store initial r6 + STR r3, [r2, #36] // Store initial r7 + STR r3, [r2, #40] // Store initial r8 + STR r3, [r2, #44] // Store initial r9 + LDR r3, [r0, #12] // Pickup stack starting address + STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] // Store initial r14 (lr) + MOV r3, #0 // Build initial register value + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc + STR r3, [r2, #68] // 0 for back-trace + MRS r1, CPSR // Pickup CPSR + BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] // Store initial CPSR + + /* Setup stack pointer. */ + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S new file mode 100644 index 000000000..6e59880dc --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S @@ -0,0 +1,168 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + + .arm + + + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + + + +/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_thread_system_return // Call _tx_thread_system_return function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + + STMDB sp!, {r4-r11, lr} // Save minimal context + + LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr + LDR r5, [r4] // Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r5, #144] // Pickup the VFP enabled flag + CMP r1, #0 // Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save // No, skip VFP solicited save + VMRS r1, FPSCR // Pickup the FPSCR + STR r1, [sp, #-4]! // Save FPSCR + VSTMDB sp!, {D16-D31} // Save D16-D31 + VSTMDB sp!, {D8-D15} // Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 // Build a solicited stack type + MRS r1, CPSR // Pickup the CPSR + STMDB sp!, {r0-r1} // Save type and CPSR + + /* Lockout interrupts. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#else + CPSID i // Disable IRQ interrupts +#endif + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + BL _tx_execution_thread_exit // Call the thread exit function +#endif + MOV r3, r4 // Pickup address of current ptr + MOV r0, r5 // Pickup current thread pointer + LDR r2, =_tx_timer_time_slice // Pickup address of time slice + LDR r1, [r2] // Pickup current time slice + + /* Save current stack and switch to system stack. */ + + STR sp, [r0, #8] // Save thread stack pointer + + /* Determine if the time-slice is active. */ + + MOV r4, #0 // Build clear value + CMP r1, #0 // Is a time-slice active? + BEQ __tx_thread_dont_save_ts // No, don't save the time-slice + + /* Save time-slice for the thread and clear the current time-slice. */ + + STR r4, [r2] // Clear time-slice + STR r1, [r0, #24] // Save current time-slice + +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + + STR r4, [r3] // Clear current thread pointer + B _tx_thread_schedule // Jump to scheduler! diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_vectored_context_save.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_vectored_context_save.S new file mode 100644 index 000000000..495e850ae --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_vectored_context_save.S @@ -0,0 +1,171 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_execution_isr_enter + + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_vectored_context_save ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state // Pickup address of system state variable + LDR r2, [r3, #0] // Pickup system state + CMP r2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3, #0] // Store it back in the variable + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Return to the ISR. */ + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + MOV pc, lr // Return to caller + +__tx_thread_not_nested_save: + + /* Otherwise, not nested, check to see if a thread was running. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3, #0] // Store it back in the variable + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1, #0] // Pickup current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Save the current stack pointer in the thread's control block. */ + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + MOV pc, lr // Return to caller + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + ADD sp, sp, #32 // Recover saved registers + MOV pc, lr // Return to caller diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_timer_interrupt.S b/ports_arch/ARMv7-A/threadx/common/src/tx_timer_interrupt.S new file mode 100644 index 000000000..1a4bc73b1 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_timer_interrupt.S @@ -0,0 +1,237 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + + .arm + + +/* Define Assembly language external references... */ + + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + + + +/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_timer_interrupt // Call _tx_timer_interrupt function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1] // Store new system clock + + /* Test for time-slice expiration. */ + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3] // Pickup time-slice + CMP r2, #0 // Is it non-active? + BEQ __tx_timer_no_time_slice // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3] // Store new time-slice value + + /* Check for expiration. */ + + CMP r2, #0 // Has it expired? + BNE __tx_timer_no_time_slice // No, skip expiration processing + + /* Set the time-slice expired flag. */ + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3] // Set time-slice expiration flag + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1] // Pickup current timer + LDR r2, [r0] // Pickup timer list entry + CMP r2, #0 // Is there anything in the list? + BEQ __tx_timer_no_timer // No, just increment the timer + + /* Set expiration flag. */ + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3] // Set expired flag + B __tx_timer_done // Finished timer processing + +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + ADD r0, r0, #4 // Move to next timer + + /* Check for wraparound. */ + + LDR r3, =_tx_timer_list_end // Pickup address of timer list end + LDR r2, [r3] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wraparound logic + + /* Wrap to beginning of list. */ + + LDR r3, =_tx_timer_list_start // Pickup address of timer list start + LDR r0, [r3] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1] // Store new current timer pointer + +__tx_timer_done: + + /* See if anything has expired. */ + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + LDR r2, [r3] // Pickup time-slice expired flag + CMP r2, #0 // Did a time-slice expire? + BNE __tx_something_expired // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup address of other expired flag + LDR r0, [r1] // Pickup timer expired flag + CMP r0, #0 // Did a timer expire? + BEQ __tx_timer_nothing_expired // No, nothing expired + +__tx_something_expired: + + STMDB sp!, {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + + LDR r1, =_tx_timer_expired // Pickup address of expired flag + LDR r0, [r1] // Pickup timer expired flag + CMP r0, #0 // Check for timer expiration + BEQ __tx_timer_dont_activate // If not set, skip timer activation + + /* Process timer expiration. */ + BL _tx_timer_expiration_process // Call the timer expiration handling routine + +__tx_timer_dont_activate: + + /* Did time slice expire? */ + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of time-slice expired + LDR r2, [r3] // Pickup the actual flag + CMP r2, #0 // See if the flag is set + BEQ __tx_timer_not_ts_expiration // No, skip time-slice processing + + /* Time slice interrupted thread. */ + + BL _tx_thread_time_slice // Call time-slice processing + +__tx_timer_not_ts_expiration: + + LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment + +__tx_timer_nothing_expired: + +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif diff --git a/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/sample_threadx.c b/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/sample_threadx.c new file mode 100644 index 000000000..8c61de065 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/tx_initialize_low_level.s b/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/tx_initialize_low_level.s new file mode 100644 index 000000000..f7f334d08 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/tx_initialize_low_level.s @@ -0,0 +1,370 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 // Disable IRQ & FIQ interrupts +FIQ_MODE EQU 0xD1 // FIQ mode +IRQ_MODE EQU 0xD2 // IRQ mode +SVC_MODE EQU 0xD3 // SVC mode +SYS_MODE EQU 0xDF // SYS mode + ELSE +DISABLE_INTS EQU 0x80 // Disable IRQ interrupts +FIQ_MODE EQU 0x91 // FIQ mode +IRQ_MODE EQU 0x92 // IRQ mode +SVC_MODE EQU 0x93 // SVC mode +SYS_MODE EQU 0x9F // SYS mode + ENDIF +HEAP_SIZE EQU 4096 // Heap size +FIQ_STACK_SIZE EQU 512 // FIQ stack size +SYS_STACK_SIZE EQU 1024 // SYS stack size (used for nested interrupts) +IRQ_STACK_SIZE EQU 1024 // IRQ stack size + +VFPEnable EQU 0x40000000 // VFP enable value + + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IF :DEF:TX_ENABLE_FIQ_SUPPORT + IMPORT _tx_thread_fiq_context_save + IMPORT _tx_thread_fiq_context_restore + ENDIF + IF :DEF:TX_ENABLE_IRQ_NESTING + IMPORT _tx_thread_irq_nesting_start + IMPORT _tx_thread_irq_nesting_end + ENDIF + IF :DEF:TX_ENABLE_FIQ_NESTING + IMPORT _tx_thread_fiq_nesting_start + IMPORT _tx_thread_fiq_nesting_end + ENDIF + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT _tx_version_id + IMPORT _tx_build_options + IMPORT |Image$$ZI$$Limit| + + AREA Init, CODE, READONLY + +/* Define the default Cortex-A7 vector area. This should be located or copied to 0. */ + + EXPORT __vectors +__vectors + LDR pc,=Reset_Vector // Reset goes to startup function + LDR pc,=__tx_undefined // Undefined handler + LDR pc,=__tx_swi_interrupt // Software interrupt handler + LDR pc,=__tx_prefetch_handler // Prefetch exception handler + LDR pc,=__tx_abort_handler // Abort exception handler + LDR pc,=__tx_reserved_handler // Reserved exception handler + LDR pc,=__tx_irq_handler // IRQ interrupt handler + LDR pc,=__tx_fiq_handler // FIQ interrupt handler + + EXPORT Reset_Vector +Reset_Vector + + IF {TARGET_FPU_VFP} = {TRUE} + MRC p15, 0, r1, c1, c0, 2 // r1 = Access Control Register + ORR r1, r1, #(0xf << 20) // Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 // Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 // Flush prefetch buffer because of FMXR below and + // CP 10 & 11 were only just enabled + MOV r0, #VFPEnable // Enable VFP itself + FMXR FPEXC, r0 // FPEXC = r0 + ENDIF + + B __main + + AREA ||.text||, CODE, READONLY +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + + EXPORT _tx_initialize_low_level +_tx_initialize_low_level + + /****** NOTE ****** We must be in SVC MODE at this point. Some monitors + enter this routine in USER mode and require a software interrupt to + change into SVC mode. */ + + LDR r1, =|Image$$ZI$$Limit| // Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE // Pickup the heap size + ADD r1, r2, r1 // Setup heap limit + ADD r1, r1, #4 // Setup stack limit + + IF :DEF:TX_ENABLE_IRQ_NESTING + /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE // Pickup stack size + MOV r3, #SYS_MODE // Build SYS mode CPSR + MSR CPSR_c, r3 // Enter SYS mode + ADD r1, r1, r2 // Calculate start of SYS stack + BIC r1, r1, #7 // Ensure 8-byte alignment + MOV sp, r1 // Setup SYS stack pointer + ENDIF + + LDR r2, =FIQ_STACK_SIZE // Pickup stack size + MOV r0, #FIQ_MODE // Build FIQ mode CPSR + MSR CPSR_c, r0 // Enter FIQ mode + ADD r1, r1, r2 // Calculate start of FIQ stack + BIC r1, r1, #7 // Ensure 8-byte alignment + MOV sp, r1 // Setup FIQ stack pointer + MOV sl, #0 // Clear sl + MOV fp, #0 // Clear fp + LDR r2, =IRQ_STACK_SIZE // Pickup IRQ (system stack size) + MOV r0, #IRQ_MODE // Build IRQ mode CPSR + MSR CPSR_c, r0 // Enter IRQ mode + ADD r1, r1, r2 // Calculate start of IRQ stack + BIC r1, r1, #7 // Ensure 8-byte alignment + MOV sp, r1 // Setup IRQ stack pointer + MOV r0, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r0 // Enter SVC mode + LDR r3, =_tx_thread_system_stack_ptr // Pickup stack pointer + STR r1, [r3, #0] // Save the system stack + + /* Save the system stack pointer. */ + + LDR r1, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + LDR r0, [r1, #0] // Pickup system stack + ADD r0, r0, #4 // Increment to next free word + + LDR r2, =_tx_initialize_unused_memory // Pickup unused memory ptr address + STR r0, [r2, #0] // Save first free memory address + + IF {INTER} = {TRUE} + BX lr // Return to caller + ELSE + MOV pc, lr // Return to caller + ENDIF + +/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This + routine will set the initial stack to use the ThreadX IRQ & FIQ & + (optionally SYS) stack areas. */ + + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR r0, =|Image$$ZI$$Limit| // Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE // Pickup the heap size + ADD r2, r2, r0 // Setup heap limit + ADD r3, r2, #4 // Setup stack limit + MOV r1, r3 // Setup start of stack + IF :DEF:TX_ENABLE_IRQ_NESTING + LDR r12, =SYS_STACK_SIZE // Pickup IRQ system stack + ADD r1, r1, r12 // Setup the return system stack + BIC r1, r1, #7 // Ensure 8-byte alignment + ENDIF + LDR r12, =FIQ_STACK_SIZE // Pickup FIQ stack size + ADD r1, r1, r12 // Setup the return system stack + BIC r1, r1, #7 // Ensure 8-byte alignment + LDR r12, =IRQ_STACK_SIZE // Pickup IRQ system stack + ADD r1, r1, r12 // Setup the return system stack + BIC r1, r1, #7 // Ensure 8-byte alignment + IF {INTER} = {TRUE} + BX lr // Return to caller + ELSE + MOV pc, lr // Return to caller + ENDIF + + +/* Define shells for each of the interrupt vectors. */ + + EXPORT __tx_undefined +__tx_undefined + B __tx_undefined // Undefined handler + + EXPORT __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt // Software interrupt handler + + EXPORT __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler // Prefetch exception handler + + EXPORT __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler // Abort exception handler + + EXPORT __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler // Reserved exception handler + + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + + BL _tx_timer_interrupt // Timer interrupt handler +_tx_not_timer_interrupt + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start + ENDIF + + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end + ENDIF + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + + /* This is an example of a vectored IRQ handler. */ + + EXPORT __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler + + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ + + /* Jump to context restore to restore system context. */ + + IF :DEF:TX_ENABLE_FIQ_SUPPORT + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. + + NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start + ENDIF + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end + ENDIF + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + ELSE + EXPORT __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler // FIQ interrupt handler + ENDIF + + /* Reference build options and version ID to ensure they come in. */ + + LDR r2, =_tx_build_options // Pickup build options variable address + LDR r0, [r2, #0] // Pickup build options content + LDR r2, =_tx_version_id // Pickup version ID variable address + LDR r0, [r2, #0] // Pickup version ID content + + + END + diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/.cproject b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 000000000..e75dac72f --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,176 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/.project b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/.project new file mode 100644 index 000000000..ed4c08857 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/.project @@ -0,0 +1,27 @@ + + + sample_threadx + + + tx + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.c b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 000000000..8c61de065 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.launch b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.launch new file mode 100644 index 000000000..0bc5b11b0 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.launch @@ -0,0 +1,188 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 000000000..d23881cd7 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,44 @@ +;******************************************************* +; Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for ARMv7-A bare-metal example on Versatile Express + +; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. + + +SDRAM 0x80000000 0x20000000 +{ + VECTORS +0 + { + * (VECTORS, +FIRST) ; Vector table and other (assembler) startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + } + + RO_CODE +0 + { * (+RO-CODE) } ; Application RO code (.text) + + RO_DATA +0 + { * (+RO-DATA) } ; Application RO data (.constdata) + + RW_DATA +0 + { * (+RW) } ; Application RW data (.data) + + ZI_DATA +0 + { * (+ZI) } ; Application ZI data (.bss) + + ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap + { } + + ARM_LIB_STACK 0x80090000 EMPTY 0x00010000 ; Application (SVC mode) stack + { } + +; IRQ_STACK 0x800A0000 EMPTY -0x00010000 ; IRQ mode stack +; { } + + TTB 0x80100000 EMPTY 0x4000 ; Level-1 Translation Table for MMU + { } +} diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/startup.S b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/startup.S new file mode 100644 index 000000000..670fadb9f --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/startup.S @@ -0,0 +1,397 @@ +//---------------------------------------------------------------- +// ARMv7-A Embedded example - Startup Code +// +// Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +//---------------------------------------------------------------- + +// Standard definitions of mode bits and interrupt (I & F) flags in PSRs + +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F + +#define I_Bit 0x80 // When I bit is set, IRQ is disabled +#define F_Bit 0x40 // When F bit is set, FIQ is disabled + + + .section VECTORS, "ax" + .align 3 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + +//---------------------------------------------------------------- +// Entry point for the Reset handler +//---------------------------------------------------------------- + + .global Vectors + +//---------------------------------------------------------------- +// Exception Vector Table +//---------------------------------------------------------------- +// Note: LDR PC instructions are used here, though branch (B) instructions +// could also be used, unless the exception handlers are >32MB away. + +Vectors: + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SVC_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + LDR PC, Hypervisor_Addr + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + + + .balign 4 +Reset_Addr: + .word Reset_Handler +Undefined_Addr: + .word __tx_undefined +SVC_Addr: + .word __tx_swi_interrupt +Prefetch_Addr: + .word __tx_prefetch_handler +Abort_Addr: + .word __tx_abort_handler +Hypervisor_Addr: + .word __tx_reserved_handler +IRQ_Addr: + .word __tx_irq_handler +FIQ_Addr: + .word __tx_fiq_handler + + +//---------------------------------------------------------------- +// Exception Handlers +//---------------------------------------------------------------- + +Undefined_Handler: + B Undefined_Handler +SVC_Handler: + B SVC_Handler +Prefetch_Handler: + B Prefetch_Handler +Abort_Handler: + B Abort_Handler +Hypervisor_Handler: + B Hypervisor_Handler +IRQ_Handler: + B IRQ_Handler +FIQ_Handler: + B FIQ_Handler + + +//---------------------------------------------------------------- +// Reset Handler +//---------------------------------------------------------------- +Reset_Handler: + +//---------------------------------------------------------------- +// Disable caches and MMU in case they were left enabled from an earlier run +// This does not need to be done from a cold reset +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU + BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + +// The MMU is enabled later, before calling main(). Caches are enabled inside main(), +// after the MMU has been enabled and scatterloading has been performed. + +//---------------------------------------------------------------- +// ACTLR.SMP bit must be set before the caches and MMU are enabled, +// or any cache and TLB maintenance operations are performed, even for single-core +//---------------------------------------------------------------- + MRC p15, 0, r0, c1, c0, 1 // Read ACTLR + ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit + MCR p15, 0, r0, c1, c0, 1 // Write ACTLR + ISB + +//---------------------------------------------------------------- +// Invalidate Data and Instruction TLBs and branch predictor +// This does not need to be done from a cold reset +//---------------------------------------------------------------- + + MOV r0,#0 + MCR p15, 0, r0, c8, c7, 0 // I-TLB and D-TLB invalidation + MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array + +//---------------------------------------------------------------- +// Initialize Supervisor Mode Stack +// Note stack must be 8 byte aligned. +//---------------------------------------------------------------- + + LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit + +//---------------------------------------------------------------- +// Disable loop-buffer to fix errata on A15 r0p0 +//---------------------------------------------------------------- + MRC p15, 0, r0, c0, c0, 0 // Read main ID register MIDR + MOV r1, r0, lsr #4 // Extract Primary Part Number + LDR r2, =0xFFF + AND r1, r1, r2 + LDR r2, =0xC0F + CMP r1, r2 // Is this an A15? + BNE notA15r0p0 // Jump if not A15 + AND r5, r0, #0x00f00000 // Variant + AND r6, r0, #0x0000000f // Revision + ORRS r6, r6, r5 // Combine variant and revision + BNE notA15r0p0 // Jump if not r0p0 + MRC p15, 0, r0, c1, c0, 1 // Read Aux Ctrl Reg + ORR r0, r0, #(1 << 1) // Set bit 1 to Disable Loop Buffer + MCR p15, 0, r0, c1, c0, 1 // Write Aux Ctrl Reg + ISB +notA15r0p0: + +//---------------------------------------------------------------- +// Set Vector Base Address Register (VBAR) to point to this application's vector table +//---------------------------------------------------------------- + + LDR r0, =Vectors + MCR p15, 0, r0, c12, c0, 0 + +//---------------------------------------------------------------- +// Cache Invalidation code for ARMv7-A +// The caches, MMU and BTB do not need post-reset invalidation on Cortex-A7, +// but forcing a cache invalidation makes the code more portable to other CPUs (e.g. Cortex-A9) +//---------------------------------------------------------------- + + // Invalidate L1 Instruction Cache + + MRC p15, 1, r0, c0, c0, 1 // Read Cache Level ID Register (CLIDR) + TST r0, #0x3 // Harvard Cache? + MOV r0, #0 // SBZ + MCRNE p15, 0, r0, c7, c5, 0 // ICIALLU - Invalidate instruction cache and flush branch target cache + + // Invalidate Data/Unified Caches + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x07000000 // Extract coherency level + MOV r3, r3, LSR #23 // Total cache levels << 1 + BEQ Finished // If 0, no need to clean + + MOV r10, #0 // R10 holds current cache level << 1 +Loop1: + ADD r2, r10, r10, LSR #1 // R2 holds cache "Set" position + MOV r1, r0, LSR r2 // Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 // Isolate those lower 3 bits + CMP r1, #2 + BLT Skip // No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 // Write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // Reads current Cache Size ID register + AND r2, r1, #7 // Extract the line length field + ADD r2, r2, #4 // Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +Loop2: + MOV r9, r4 // R9 working copy of the max way size (right aligned) + +Loop3: + ORR r11, r10, r9, LSL r5 // Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // Factor in the Set number + MCR p15, 0, r11, c7, c6, 2 // Invalidate by Set/Way + SUBS r9, r9, #1 // Decrement the Way number + BGE Loop3 + SUBS r7, r7, #1 // Decrement the Set number + BGE Loop2 +Skip: + ADD r10, r10, #2 // Increment the cache number + CMP r3, r10 + BGT Loop1 + +Finished: + + +//---------------------------------------------------------------- +// MMU Configuration +// Set translation table base +//---------------------------------------------------------------- + + // Two translation tables are supported, TTBR0 and TTBR1 + // Configure translation table base (TTB) control register cp15,c2 + // to a value of all zeros, indicates we are using TTB register 0. + + MOV r0,#0x0 + MCR p15, 0, r0, c2, c0, 2 + + // write the address of our page table base to TTB register 0 + LDR r0,=Image$$TTB$$ZI$$Base + + MOV r1, #0x08 // RGN=b01 (outer cacheable write-back cached, write allocate) + // S=0 (translation table walk to non-shared memory) + ORR r1,r1,#0x40 // IRGN=b01 (inner cacheability for the translation table walk is Write-back Write-allocate) + + ORR r0,r0,r1 + + MCR p15, 0, r0, c2, c0, 0 + + +//---------------------------------------------------------------- +// PAGE TABLE generation + +// Generate the page tables +// Build a flat translation table for the whole address space. +// ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx + + +// 31 20 19 18 17 16 15 14 12 11 10 9 8 5 4 3 2 1 0 +// |section base address| 0 0 |nG| S |AP2| TEX | AP | P | Domain | XN | C B | 1 0| +// +// Bits[31:20] - Top 12 bits of VA is pointer into table +// nG[17]=0 - Non global, enables matching against ASID in the TLB when set. +// S[16]=0 - Indicates normal memory is shared when set. +// AP2[15]=0 +// AP[11:10]=11 - Configure for full read/write access in all modes +// TEX[14:12]=000 +// CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +// (except for the code segment descriptor, see below) +// IMPP[9]=0 - Ignored +// Domain[5:8]=1111 - Set all pages to use domain 15 +// XN[4]=1 - Execute never on Strongly-ordered memory +// Bits[1:0]=10 - Indicate entry is a 1MB section +//---------------------------------------------------------------- + LDR r0,=Image$$TTB$$ZI$$Base + LDR r1,=0xfff // loop counter + LDR r2,=0b00000000000000000000110111100010 + + // r0 contains the address of the translation table base + // r1 is loop counter + // r2 is level1 descriptor (bits 19:0) + + // use loop counter to create 4096 individual table entries. + // this writes from address 'Image$$TTB$$ZI$$Base' + + // offset 0x3FFC down to offset 0x0 in word steps (4 bytes) + +init_ttb_1: + ORR r3, r2, r1, LSL#20 // R3 now contains full level1 descriptor to write + ORR r3, r3, #0b0000000010000 // Set XN bit + STR r3, [r0, r1, LSL#2] // Str table entry at TTB base + loopcount*4 + SUBS r1, r1, #1 // Decrement loop counter + BPL init_ttb_1 + + // In this example, the 1MB section based at '__code_start' is setup specially as cacheable (write back mode). + // TEX[14:12]=001 and CB[3:2]= 11, Outer and inner write back, write allocate normal memory. + LDR r1,=Image$$VECTORS$$Base // Base physical address of code segment + LSR r1, #20 // Shift right to align to 1MB boundaries + ORR r3, r2, r1, LSL#20 // Setup the initial level1 descriptor again + ORR r3, r3, #0b0000000001100 // Set CB bits + ORR r3, r3, #0b1000000000000 // Set TEX bit 12 + STR r3, [r0, r1, LSL#2] // str table entry + +//---------------------------------------------------------------- +// Setup domain control register - Enable all domains to client mode +//---------------------------------------------------------------- + + MRC p15, 0, r0, c3, c0, 0 // Read Domain Access Control Register + LDR r0, =0x55555555 // Initialize every domain entry to b01 (client) + MCR p15, 0, r0, c3, c0, 0 // Write Domain Access Control Register + +#if defined(__ARM_NEON) || defined(__ARM_FP) +//---------------------------------------------------------------- +// Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. +// Enables Full Access i.e. in both privileged and non privileged modes +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR) + ISB + +//---------------------------------------------------------------- +// Switch on the VFP and NEON hardware +//---------------------------------------------------------------- + + MOV r0, #0x40000000 + VMSR FPEXC, r0 // Write FPEXC register, EN bit set +#endif + + +//---------------------------------------------------------------- +// Enable MMU and branch to __main +// Leaving the caches disabled until after scatter loading. +//---------------------------------------------------------------- + + LDR r12,=__main + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC r0, r0, #0x2 // Clear A bit 1 to disable strict alignment fault checking + ORR r0, r0, #0x1 // Set M bit 0 to enable MMU before scatter loading + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + +// Now the MMU is enabled, virtual to physical address translations will occur. This will affect the next +// instruction fetch. +// +// The two instructions currently in the pipeline will have been fetched before the MMU was enabled. +// The branch to __main is safe because the Virtual Address (VA) is the same as the Physical Address (PA) +// (flat mapping) of this code that enables the MMU and performs the branch + + BX r12 // Branch to __main C library entry point + + + +//---------------------------------------------------------------- +// Enable caches and branch prediction +// This code must be run from a privileged mode +//---------------------------------------------------------------- + + .section ENABLECACHES,"ax" + .align 3 + + .global enable_caches + .type enable_caches, "function" + .cfi_startproc +enable_caches: + +//---------------------------------------------------------------- +// Enable caches and branch prediction +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #(0x1 << 12) // Set I bit 12 to enable I Cache + ORR r0, r0, #(0x1 << 2) // Set C bit 2 to enable D Cache + ORR r0, r0, #(0x1 << 11) // Set Z bit 11 to enable branch prediction + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + MRC p15, 0, r0, c1, c0, 1 // Read Auxiliary Control Register + ORR r0, #2 // L2EN bit, enable L2 cache + ORR r0, r0, #(0x1 << 2) // Set DP bit 2 to enable L1 Dside prefetch + MCR p15, 0, r0, c1, c0, 1 // Write Auxiliary Control Register + ISB + + BX lr + .cfi_endproc + + .global disable_caches + .type disable_caches, "function" +disable_caches: + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + BX lr + + diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 000000000..715958f01 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,299 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .arm + +SVC_MODE = 0xD3 // Disable IRQ/FIQ SVC mode +IRQ_MODE = 0xD2 // Disable IRQ/FIQ IRQ mode +FIQ_MODE = 0xD1 // Disable IRQ/FIQ FIQ mode +SYS_MODE = 0xDF // Disable IRQ/FIQ SYS mode +FIQ_STACK_SIZE = 512 // FIQ stack size +IRQ_STACK_SIZE = 1024 // IRQ stack size +SYS_STACK_SIZE = 1024 // System stack size + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + + + +/* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .thumb + .global $_tx_initialize_low_level + .type $_tx_initialize_low_level,function +$_tx_initialize_low_level: + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_initialize_low_level // Call _tx_initialize_low_level function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level ARMV7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_initialize_low_level + .type _tx_initialize_low_level,function +_tx_initialize_low_level: + + /* We must be in SVC mode at this point! */ + + /* Setup various stack pointers. */ + + LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Get pointer to stack area + +#ifdef TX_ENABLE_IRQ_NESTING + + /* Setup the system mode stack for nested interrupt support */ + + LDR r2, =SYS_STACK_SIZE // Pickup stack size + MOV r3, #SYS_MODE // Build SYS mode CPSR + MSR CPSR_c, r3 // Enter SYS mode + SUB r1, r1, #1 // Backup 1 byte + BIC r1, r1, #7 // Ensure 8-byte alignment + MOV sp, r1 // Setup SYS stack pointer + SUB r1, r1, r2 // Calculate start of next stack +#endif + + LDR r2, =FIQ_STACK_SIZE // Pickup stack size + MOV r0, #FIQ_MODE // Build FIQ mode CPSR + MSR CPSR, r0 // Enter FIQ mode + SUB r1, r1, #1 // Backup 1 byte + BIC r1, r1, #7 // Ensure 8-byte alignment + MOV sp, r1 // Setup FIQ stack pointer + SUB r1, r1, r2 // Calculate start of next stack + LDR r2, =IRQ_STACK_SIZE // Pickup IRQ stack size + MOV r0, #IRQ_MODE // Build IRQ mode CPSR + MSR CPSR, r0 // Enter IRQ mode + SUB r1, r1, #1 // Backup 1 byte + BIC r1, r1, #7 // Ensure 8-byte alignment + MOV sp, r1 // Setup IRQ stack pointer + SUB r3, r1, r2 // Calculate end of IRQ stack + MOV r0, #SVC_MODE // Build SVC mode CPSR + MSR CPSR, r0 // Enter SVC mode + LDR r2, =Image$$ARM_LIB_STACK$$Base // Pickup stack bottom + CMP r3, r2 // Compare the current stack end with the bottom +_stack_error_loop: + BLT _stack_error_loop // If the IRQ stack exceeds the stack bottom, just sit here! + + LDR r2, =_tx_thread_system_stack_ptr // Pickup stack pointer + STR r1, [r2] // Save the system stack + + LDR r1, =Image$$ZI_DATA$$ZI$$Limit // Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory // Pickup unused memory ptr address + ADD r1, r1, #8 // Increment to next free word + STR r1, [r2] // Save first free memory address + +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif + +/* Define shells for each of the interrupt vectors. */ + + .global __tx_undefined +__tx_undefined: + B __tx_undefined // Undefined handler + + .global __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt // Software interrupt handler + + .global __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler // Prefetch exception handler + + .global __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler // Abort exception handler + + .global __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler // Reserved exception handler + + .global __tx_irq_processing_return + .type __tx_irq_processing_return,function + .global __tx_irq_handler +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + /* For debug purpose, execute the timer interrupt processing here. In + a real system, some kind of status indication would have to be checked + before the timer interrupt handler could be called. */ + + BL _tx_timer_interrupt // Timer interrupt handler + + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + + /* This is an example of a vectored IRQ handler. */ + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ + + /* Jump to context restore to restore system context. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. + + NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +#else + .global __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler // FIQ interrupt handler +#endif + + +BUILD_OPTIONS: + .word _tx_build_options // Reference to bring in +VERSION_ID: + .word _tx_version_id // Reference to bring in + + diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/tx/.cproject b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/tx/.cproject new file mode 100644 index 000000000..476321bbd --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/tx/.cproject @@ -0,0 +1,146 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/tx/.project b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/tx/.project new file mode 100644 index 000000000..863ca5cb5 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/crt0.S b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/crt0.S new file mode 100644 index 000000000..56b6c9580 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/crt0.S @@ -0,0 +1,90 @@ + +/* .text is used instead of .section .text so it works with arm-aout too. */ + .text + .code 32 + .align 0 + + .global _mainCRTStartup + .global _start + .global start +start: +_start: +_mainCRTStartup: + +/* Start by setting up a stack */ + /* Set up the stack pointer to a fixed value */ + ldr r3, .LC0 + mov sp, r3 + /* Setup a default stack-limit in case the code has been + compiled with "-mapcs-stack-check". Hard-wiring this value + is not ideal, since there is currently no support for + checking that the heap and stack have not collided, or that + this default 64k is enough for the program being executed. + However, it ensures that this simple crt0 world will not + immediately cause an overflow event: */ + sub sl, sp, #64 << 10 /* Still assumes 256bytes below sl */ + mov a2, #0 /* Second arg: fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr a1, .LC1 /* First arg: start of memory block */ + ldr a3, .LC2 + sub a3, a3, a1 /* Third arg: length of block */ + + + + bl memset + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ +#ifdef __USES_INITFINI__ + /* Some arm/elf targets use the .init and .fini sections + to create constructors and destructors, and for these + targets we need to call the _init function and arrange + for _fini to be called at program exit. */ + mov r4, r0 + mov r5, r1 +/* ldr r0, .Lfini */ + bl atexit +/* bl init */ + mov r0, r4 + mov r1, r5 +#endif + bl main + + bl exit /* Should not return. */ + + + /* For Thumb, constants must be after the code since only + positive offsets are supported for PC relative addresses. */ + + .align 0 +.LC0: +.LC1: + .word __bss_start__ +.LC2: + .word __bss_end__ +/* +#ifdef __USES_INITFINI__ +.Lfini: + .word _fini +#endif */ + /* Return ... */ +#ifdef __APCS_26__ + movs pc, lr +#else +#ifdef __THUMB_INTERWORK + bx lr +#else + mov pc, lr +#endif +#endif + + +/* Workspace for Angel calls. */ + .data +/* Data returned by monitor SWI. */ +.global __stack_base__ +HeapBase: .word 0 +HeapLimit: .word 0 +__stack_base__: .word 0 +StackLimit: .word 0 diff --git a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/reset.S b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/reset.S new file mode 100644 index 000000000..597e9d9ad --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/reset.S @@ -0,0 +1,64 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .arm + + .global _start + .global __tx_undefined + .global __tx_swi_interrupt + .global __tx_prefetch_handler + .global __tx_abort_handler + .global __tx_reserved_handler + .global __tx_irq_handler + .global __tx_fiq_handler + +/* Define the vector area. This should be located or copied to 0. */ + + .text + .global __vectors +__vectors: + + LDR pc, STARTUP // Reset goes to startup function + LDR pc, UNDEFINED // Undefined handler + LDR pc, SWI // Software interrupt handler + LDR pc, PREFETCH // Prefetch exception handler + LDR pc, ABORT // Abort exception handler + LDR pc, RESERVED // Reserved exception handler + LDR pc, IRQ // IRQ interrupt handler + LDR pc, FIQ // FIQ interrupt handler + +STARTUP: + .word _start // Reset goes to C startup function +UNDEFINED: + .word __tx_undefined // Undefined handler +SWI: + .word __tx_swi_interrupt // Software interrupt handler +PREFETCH: + .word __tx_prefetch_handler // Prefetch exception handler +ABORT: + .word __tx_abort_handler // Abort exception handler +RESERVED: + .word __tx_reserved_handler // Reserved exception handler +IRQ: + .word __tx_irq_handler // IRQ interrupt handler +FIQ: + .word __tx_fiq_handler // FIQ interrupt handler diff --git a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.c b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.c new file mode 100644 index 000000000..8c61de065 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.ld b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.ld new file mode 100644 index 000000000..3dea4e1ca --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.ld @@ -0,0 +1,239 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", + "elf32-littlearm") +OUTPUT_ARCH(arm) +/* ENTRY(_start) */ +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + . = 0x00000000; + + .vectors : {reset.o(.text) } + + /* Read-only sections, merged into text segment: */ + . = 0x00001000; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.text : + { + *(.rel.text) + *(.rel.text.*) + *(.rel.gnu.linkonce.t*) + } + .rela.text : + { + *(.rela.text) + *(.rela.text.*) + *(.rela.gnu.linkonce.t*) + } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.rodata : + { + *(.rel.rodata) + *(.rel.rodata.*) + *(.rel.gnu.linkonce.r*) + } + .rela.rodata : + { + *(.rela.rodata) + *(.rela.rodata.*) + *(.rela.gnu.linkonce.r*) + } + .rel.data : + { + *(.rel.data) + *(.rel.data.*) + *(.rel.gnu.linkonce.d*) + } + .rela.data : + { + *(.rela.data) + *(.rela.data.*) + *(.rela.gnu.linkonce.d*) + } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.sdata : + { + *(.rel.sdata) + *(.rel.sdata.*) + *(.rel.gnu.linkonce.s*) + } + .rela.sdata : + { + *(.rela.sdata) + *(.rela.sdata.*) + *(.rela.gnu.linkonce.s*) + } + .rel.sbss : { *(.rel.sbss) } + .rela.sbss : { *(.rela.sbss) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.text.*) + *(.stub) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + *(.glue_7t) *(.glue_7) + } =0 + .init : + { + KEEP (*(.init)) + } =0 + _etext = .; + PROVIDE (etext = .); + .fini : + { + KEEP (*(.fini)) + } =0 + .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) } + .rodata1 : { *(.rodata1) } + .eh_frame_hdr : { *(.eh_frame_hdr) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(256) + (. & (256 - 1)); + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + SORT(CONSTRUCTORS) + } + .data1 : { *(.data1) } + .eh_frame : { KEEP (*(.eh_frame)) } + .gcc_except_table : { *(.gcc_except_table) } + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + .jcr : { KEEP (*(.jcr)) } + .got : { *(.got.plt) *(.got) } + .dynamic : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + __bss_start__ = .; + .sbss : + { + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.scommon) + } + .bss : + { + *(.dynbss) + *(.bss) + *(.bss.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); + } + . = ALIGN(32 / 8); + + _bss_end__ = . ; __bss_end__ = . ; + PROVIDE (end = .); + + .stack : + { + + _stack_bottom = ABSOLUTE(.) ; + + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + SYS stack if nested interrupts are enabled. */ + . = ALIGN(8) ; + . += 4096 ; + _sp = . - 16 ; + _stack_top = ABSOLUTE(.) ; + } + + _end = .; __end__ = . ; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* These must appear regardless of . */ +} diff --git a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/tx_initialize_low_level.S b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/tx_initialize_low_level.S new file mode 100644 index 000000000..4b324e0ac --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/tx_initialize_low_level.S @@ -0,0 +1,311 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + + .arm + +SVC_MODE = 0xD3 // Disable IRQ/FIQ SVC mode +IRQ_MODE = 0xD2 // Disable IRQ/FIQ IRQ mode +FIQ_MODE = 0xD1 // Disable IRQ/FIQ FIQ mode +SYS_MODE = 0xDF // Disable IRQ/FIQ SYS mode +FIQ_STACK_SIZE = 512 // FIQ stack size +IRQ_STACK_SIZE = 1024 // IRQ stack size +SYS_STACK_SIZE = 1024 // System stack size + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + .global _end + .global _sp + .global _stack_bottom + + +/* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .thumb + .global $_tx_initialize_low_level + .type $_tx_initialize_low_level,function +$_tx_initialize_low_level: + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_initialize_low_level // Call _tx_initialize_low_level function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level ARMv7-A */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ + .global _tx_initialize_low_level + .type _tx_initialize_low_level,function +_tx_initialize_low_level: + + /* We must be in SVC mode at this point! */ + + /* Setup various stack pointers. */ + + LDR r1, =_sp // Get pointer to stack area + +#ifdef TX_ENABLE_IRQ_NESTING + + /* Setup the system mode stack for nested interrupt support */ + + LDR r2, =SYS_STACK_SIZE // Pickup stack size + MOV r3, #SYS_MODE // Build SYS mode CPSR + MSR CPSR_c, r3 // Enter SYS mode + SUB r1, r1, #1 // Backup 1 byte + BIC r1, r1, #7 // Ensure 8-byte alignment + MOV sp, r1 // Setup SYS stack pointer + SUB r1, r1, r2 // Calculate start of next stack +#endif + + LDR r2, =FIQ_STACK_SIZE // Pickup stack size + MOV r0, #FIQ_MODE // Build FIQ mode CPSR + MSR CPSR, r0 // Enter FIQ mode + SUB r1, r1, #1 // Backup 1 byte + BIC r1, r1, #7 // Ensure 8-byte alignment + MOV sp, r1 // Setup FIQ stack pointer + SUB r1, r1, r2 // Calculate start of next stack + LDR r2, =IRQ_STACK_SIZE // Pickup IRQ stack size + MOV r0, #IRQ_MODE // Build IRQ mode CPSR + MSR CPSR, r0 // Enter IRQ mode + SUB r1, r1, #1 // Backup 1 byte + BIC r1, r1, #7 // Ensure 8-byte alignment + MOV sp, r1 // Setup IRQ stack pointer + SUB r3, r1, r2 // Calculate end of IRQ stack + MOV r0, #SVC_MODE // Build SVC mode CPSR + MSR CPSR, r0 // Enter SVC mode + LDR r2, =_stack_bottom // Pickup stack bottom + CMP r3, r2 // Compare the current stack end with the bottom +_stack_error_loop: + BLT _stack_error_loop // If the IRQ stack exceeds the stack bottom, just sit here! + + LDR r2, =_tx_thread_system_stack_ptr // Pickup stack pointer + STR r1, [r2] // Save the system stack + + LDR r1, =_end // Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory // Pickup unused memory ptr address + ADD r1, r1, #8 // Increment to next free word + STR r1, [r2] // Save first free memory address + +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif + +/* Define shells for each of the interrupt vectors. */ + + .global __tx_undefined +__tx_undefined: + B __tx_undefined // Undefined handler + + .global __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt // Software interrupt handler + + .global __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler // Prefetch exception handler + + .global __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler // Abort exception handler + + .global __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler // Reserved exception handler + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +// + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + /* For debug purpose, execute the timer interrupt processing here. In + a real system, some kind of status indication would have to be checked + before the timer interrupt handler could be called. */ + + BL _tx_timer_interrupt // Timer interrupt handler + + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + + /* This is an example of a vectored IRQ handler. */ + + + + /* Save initial context and call context save to prepare for + vectored ISR execution. */ + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ + + + +#ifdef TX_ENABLE_FIQ_SUPPORT + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. + + NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +#else + .global __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler // FIQ interrupt handler +#endif + + +BUILD_OPTIONS: + .word _tx_build_options // Reference to bring in +VERSION_ID: + .word _tx_version_id // Reference to bring in + + + diff --git a/ports_arch/ARMv7-A/threadx/ports/iar/example_build/azure_rtos.eww b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/azure_rtos.eww new file mode 100644 index 000000000..17e0d3292 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/azure_rtos.eww @@ -0,0 +1,13 @@ + + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\tx.ewp + + + + + diff --git a/ports_arch/ARMv7-A/threadx/ports/iar/example_build/cstartup.s b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/cstartup.s new file mode 100644 index 000000000..b4ed8f87f --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/cstartup.s @@ -0,0 +1,156 @@ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 14520 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __vector_0x14 + PUBLIC __iar_program_start + EXTERN __tx_undefined + EXTERN __tx_swi_interrupt + EXTERN __tx_prefetch_handler + EXTERN __tx_abort_handler + EXTERN __tx_irq_handler + EXTERN __tx_fiq_handler + + ARM +__vector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort +__vector_0x14: + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD __tx_undefined +SWI_Addr: DCD __tx_swi_interrupt +Prefetch_Addr: DCD __tx_prefetch_handler +Abort_Addr: DCD __tx_abort_handler +IRQ_Addr: DCD __tx_irq_handler +FIQ_Addr: DCD __tx_fiq_handler + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reser execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + +; PUBLIC ?cstartup + EXTERN ?main + REQUIRE __vector + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR + +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + + + MRS r0, cpsr ; Original PSR value + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + +#ifdef __ARMVFP__ + MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register + ORR r1, r1, #(0xf << 20) ; Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 ; Flush prefetch buffer because of FMXR below and + ; CP 10 & 11 were only just enabled + MOV r0, #0x40000000 ; Enable VFP itself + FMXR FPEXC, r0 ; FPEXC = r0 +#endif + +; +; Add more initialization here +; + +; Continue to ?main for C-level initialization. + + B ?main + + END + + + diff --git a/ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.c b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.c new file mode 100644 index 000000000..02183317e --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.c @@ -0,0 +1,372 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +UCHAR memory_pool[DEMO_BYTE_POOL_SIZE]; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.ewd b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.ewd new file mode 100644 index 000000000..af953994b --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + 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@@ -0,0 +1,2130 @@ + + + 3 + + Debug + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 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/dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/sample_threadx.icf @@ -0,0 +1,49 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x80; +define symbol __ICFEDIT_region_ROM_end__ = 0x1FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x100000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_size_freemem__ = 0x100000; + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_freemem = mem:[from 0x200000 to 0x300000]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; + +place in RAM_region { last section FREE_MEM}; \ No newline at end of file diff --git a/ports_arch/ARMv7-A/threadx/ports/iar/example_build/tx.ewp b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/tx.ewp new file mode 100644 index 000000000..ef9fb4749 --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/tx.ewp @@ -0,0 +1,2763 @@ + + + 3 + + Debug + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\common\inc\tx_user.h + + + + src + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_allocate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_release.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_allocate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_search.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_release.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_set.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_set_notify.c + + + $PROJ_DIR$\..\src\tx_iar.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_initialize_high_level.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_initialize_kernel_enter.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_initialize_kernel_setup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_priority_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_flush.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_front_send.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_receive.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_send.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_send_notify.c + + + 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$PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_exit_insert.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_register.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_unregister.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_user_event_insert.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_block_allocate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_block_release.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_allocate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_release.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_flush.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_front_send.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_receive.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_ceiling_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_entry_exit_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_preemption_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_priority_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_relinquish.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_reset.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c + + + diff --git a/ports_arch/ARMv7-A/threadx/ports/iar/example_build/tx_initialize_low_level.s b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/tx_initialize_low_level.s new file mode 100644 index 000000000..6fd73564d --- /dev/null +++ b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,287 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +SVC_MODE DEFINE 0xD3 // Disable irq,fiq SVC mode +IRQ_MODE DEFINE 0xD2 // Disable irq,fiq IRQ mode +FIQ_MODE DEFINE 0xD1 // Disable irq,fiq FIQ mode +SYS_MODE DEFINE 0xDF // Disable irq,fiq SYS mode + + + + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_thread_context_save + EXTERN _tx_thread_context_restore +#ifdef TX_ENABLE_FIQ_SUPPORT + EXTERN _tx_thread_fiq_context_save + EXTERN _tx_thread_fiq_context_restore +#endif +#ifdef TX_ENABLE_IRQ_NESTING + EXTERN _tx_thread_irq_nesting_start + EXTERN _tx_thread_irq_nesting_end +#endif +#ifdef TX_ENABLE_FIQ_NESTING + EXTERN _tx_thread_fiq_nesting_start + EXTERN _tx_thread_fiq_nesting_end +#endif + EXTERN _tx_timer_interrupt + EXTERN ?cstartup + EXTERN _tx_build_options + EXTERN _tx_version_id + +/* Define the FREE_MEM segment that will specify where free memory is + defined. This must also be located in at the end of other RAM segments + in the linker control file. The value of this segment is what is passed + to tx_application_define. */ + + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 + + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/* */ +/**************************************************************************/ +//VOID _tx_initialize_low_level(VOID) +//{ + RSEG .text:CODE:NOROOT(2) + CODE32 + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level + + /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ + + /* Remember the stack pointer, link register, and switch to SVC mode. */ + + MOV r0, sp // Remember the SP + MOV r1, lr // Remember the LR + MOV r3, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_cxsf, r3 // Switch to SVC mode + MOV sp, r0 // Inherit the stack pointer setup by cstartup + MOV lr, r1 // Inherit the link register + + /* Pickup the start of free memory. */ + + LDR r0, =__tx_free_memory_start // Get end of non-initialized RAM area + + LDR r2, =_tx_initialize_unused_memory // Pickup unused memory ptr address + STR r0, [r2, #0] // Save first free memory address + + /* Setup Timer for periodic interrupts. */ + + /* Done, return to caller. */ + +#ifdef TX_THUMB + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif + +/* Define shells for each of the interrupt vectors. */ + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_undefined +__tx_undefined + B __tx_undefined // Undefined handler + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt // Software interrupt handler + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler // Prefetch exception handler + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler // Abort exception handler + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler // Reserved exception handler + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + /* For debug purpose, execute the timer interrupt processing here. In + a real system, some kind of status indication would have to be checked + before the timer interrupt handler could be called. */ + + BL _tx_timer_interrupt // Timer interrupt handler + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ + + + /* Application IRQ handler is called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. + + NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +#else + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler // FIQ interrupt handler +#endif + + +BUILD_OPTIONS + DC32 _tx_build_options // Reference to ensure it comes in +VERSION_ID + DC32 _tx_version_id // Reference to ensure it comes in + END + diff --git a/ports_arch/ARMv7-A/update.ps1 b/ports_arch/ARMv7-A/update.ps1 new file mode 100644 index 000000000..c444f1d6e --- /dev/null +++ b/ports_arch/ARMv7-A/update.ps1 @@ -0,0 +1,183 @@ +<# +.SYNOPSIS + Update the ARMv7-A ports from the generic ARMv7-A port. + +.DESCRIPTION + Generate ports, examples and tests from common files. + +.EXAMPLE + To update the ThreadX ports for the source tree run: + pwsh -Command .\update.ps1 -PortSets tx -CopyCommonFiles -CopyPortFiles -CopyExample -PatchFiles + + To update the ThreadX ports for the test tree run: + pwsh -Command .\update.ps1 -PortSets tx -CopyCommonFiles -CopyPortFiles -CopyExample -CopyValidationTest -CopyRegressionTest -PatchFiles + +.LINK + https://azure.com/rtos + +.NOTES + Author: Andres Mlinar + Date: 2021 +#> + +[CmdletBinding(PositionalBinding=$false)] Param( + + [string] + #The script root directory, if not specified it defaults to this script's directory + $ScriptDir = $PSScriptRoot, + + [Parameter(Mandatory)] + [ValidateSet( + "tx", "tx_smp", + "txm", "txm_smp" + )] + [string[]] + #Specify the flavor or flavors of ThreadX to generate. Options are: tx, tx_smp, txm, txm_smp + $PortSets, + + [switch] + #Copy common files + $CopyCommonFiles = $false, + + [switch] + #Copy port files + $CopyPortFiles = $false, + + [switch] + #Copy the example + $CopyExample = $false, + + [switch] + #Copy the validation tests + $CopyValidationTest = $false, + + [switch] + #Copy the regression tests + $CopyRegressionTest = $false, + + [switch] + #Copy port files + $PatchFiles = $false, + + [string] + #The output log directory + $LogDir = $( Join-Path $PSScriptRoot 'log' ) + +) + +Write-Host "Update the ARMv7-A ports" + +Write-Verbose ("Script directory: $ScriptDir") +Write-Verbose ("Port sets: $PortSets") +Write-Verbose ("Copy common files: $CopyCommonFiles") +Write-Verbose ("Copy port files: $CopyPortFiles") +Write-Verbose ("Copy example: $CopyExample") +Write-Verbose ("Copy validation test: $CopyValidationTest") +Write-Verbose ("Copy regression test: $CopyRegressionTest") +Write-Verbose ("Patch files: $PatchFiles") +Write-Verbose ("LogDir: $LogDir") + +$cores = @("cortex_a5", "cortex_a7", "cortex_a8", "cortex_a9", "cortex_a12", "cortex_a15", "cortex_a17") +$compilers = @("ac6", "gnu") +#$compilers = @("ac5", "ac6", "gnu", "iar") +$patches = ( + ('example_build\sample_threadx\.cproject', ( + ('value=`"cortex-a7`"', 'value=`"cortex-$($core_short_lower)`"'), + ('Cortex-A7.NoFPU', 'Cortex-$($core_short_upper).NoFPU') + )), + ('example_build\tx\.cproject', ( + ('value=`"cortex-a7`"', 'value=`"cortex-$($core_short_lower)`"'), + ('Cortex-A7.NoFPU', 'Cortex-$($core_short_upper).NoFPU') + )), + ('example_build\sample_threadx\sample_threadx.launch', ( + ('Debug Cortex-A7', 'Debug Cortex-$($core_short_upper)'), + ('VE_Cortex_A7x1', 'VE_Cortex_$($core_short_upper)x1'), + ('ve_cortex_a7x1', 've_cortex_$($core_short_lower)x1'), + ('FVP_VE_Cortex-A7x1', 'FVP_VE_Cortex-$($core_short_upper)x1') + )) +) + +# Create the log directory if it doesn't already exists +If (-Not (Test-Path -Path $LogDir -PathType Container)) { + $LogDirObject = New-Item -Path $LogDir -ItemType Directory +} + +Function Copy-FilesVerbose { + [CmdletBinding()] Param ( + [string] $source, + [string] $destination_directory + ) + Write-Verbose ("Copying common files...") + Write-Verbose ("Copy: " + $source + " -> " + $destination_directory) + Copy-Item -Path $source -Destination $destination_directory -Recurse -Force + Write-Verbose("Done.") +} + +ForEach ($PortSet in $PortSets) { + ForEach ($core in $cores) { + Switch ($PortSet) { + "tx" { $core_directory = "..\..\ports\" + $core } + "tx_smp" { $core_directory = "..\..\ports_smp\" + $core + "_smp" } + "txm" { $core_directory = "..\..\ports_module\" + $core } + "txm_smp" { $core_directory = "..\..\ports_module_smp\" + $core + "_smp" } + Default {} + } + ForEach ($compiler in $compilers) { + $compiler_directory = $core_directory + "\" + $compiler + Write-Verbose ("Compiler directory: $compiler_directory") + $compiler_directory_object = New-Item -Path $compiler_directory -ItemType "directory" -Force + + $destination_directory = $compiler_directory + + If ($CopyCommonFiles) { + Copy-FilesVerbose -source "threadx\common\*" -destination_directory $destination_directory + } + + If ($CopyPortFiles) { + Copy-FilesVerbose -source "threadx\ports\$compiler\*" -destination_directory $destination_directory + } + + If ($PortSet -eq 'tx_smp') { + If ($CopyCommonFiles) { + Copy-FilesVerbose -source "threadx_smp\common\*" -destination_directory $destination_directory + } + If ($CopyPortFiles) { + Copy-FilesVerbose -source "threadx_smp\ports\$compiler\*" -destination_directory $destination_directory + } + } + + If ($PortSet -eq 'txm') { + } + + If ($PortSet -eq 'txm_smp') { + } + + If ($PatchFiles) { + ForEach ($patch in $patches) { + $core_short = $core -Replace "cortex_","" + $core_short_upper = $core_short.ToUpper() + $core_short_lower = $core_short.ToLower() + ForEach ($patch in $patches) { + $path = $destination_directory + "\" + $patch[0] + Write-Verbose("Patching file: $path") + If (Test-Path -Path $path -PathType leaf) { + $content = Get-Content -Path $path + ForEach ($replacement in $patch[1]) { + $original = $replacement[0] + $substitute = $replacement[1] + $original = $ExecutionContext.InvokeCommand.ExpandString($original) + $substitute = $ExecutionContext.InvokeCommand.ExpandString($substitute) + Write-Verbose("`tpatch: `"$original`" -> `"$substitute`"") + $content = $content -creplace $original,$substitute + } + Set-Content -Path $path -Value $content -Encoding ascii + Write-Verbose("Patched.") + } Else { + Write-Verbose("File not found.") + } + } + } + } + } + } +} From 7f4f628db8877c0bc1bb2aaf67948064fc115ec1 Mon Sep 17 00:00:00 2001 From: Tiejun Zhou Date: Wed, 19 Apr 2023 08:46:45 +0000 Subject: [PATCH 2/3] Add tx_user.h to GNU port assembly files --- ports/cortex_a12/ac6/src/tx_thread_context_restore.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_thread_context_save.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_thread_fiq_context_restore.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_thread_fiq_context_save.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_thread_schedule.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_thread_stack_build.S | 9 ++++++++- ports/cortex_a12/ac6/src/tx_thread_system_return.S | 8 +++++++- .../cortex_a12/ac6/src/tx_thread_vectored_context_save.S | 8 +++++++- ports/cortex_a12/ac6/src/tx_timer_interrupt.S | 8 +++++++- .../gnu/example_build/tx_initialize_low_level.S | 8 +++++++- ports/cortex_a12/gnu/src/tx_thread_context_restore.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_context_save.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_schedule.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_stack_build.S | 6 +++--- ports/cortex_a12/gnu/src/tx_thread_system_return.S | 6 +++--- .../cortex_a12/gnu/src/tx_thread_vectored_context_save.S | 6 +++--- ports/cortex_a12/gnu/src/tx_timer_interrupt.S | 6 +++--- ports/cortex_a15/ac6/src/tx_thread_context_restore.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_thread_context_save.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_thread_schedule.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_thread_stack_build.S | 9 ++++++++- ports/cortex_a15/ac6/src/tx_thread_system_return.S | 8 +++++++- .../cortex_a15/ac6/src/tx_thread_vectored_context_save.S | 8 +++++++- ports/cortex_a15/ac6/src/tx_timer_interrupt.S | 8 +++++++- .../gnu/example_build/tx_initialize_low_level.S | 8 +++++++- ports/cortex_a15/gnu/src/tx_thread_context_restore.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_context_save.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_schedule.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_stack_build.S | 6 +++--- ports/cortex_a15/gnu/src/tx_thread_system_return.S | 6 +++--- .../cortex_a15/gnu/src/tx_thread_vectored_context_save.S | 6 +++--- ports/cortex_a15/gnu/src/tx_timer_interrupt.S | 6 +++--- ports/cortex_a17/ac6/src/tx_thread_context_restore.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_thread_context_save.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_thread_fiq_context_restore.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_thread_fiq_context_save.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_thread_schedule.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_thread_stack_build.S | 9 ++++++++- ports/cortex_a17/ac6/src/tx_thread_system_return.S | 8 +++++++- .../cortex_a17/ac6/src/tx_thread_vectored_context_save.S | 8 +++++++- ports/cortex_a17/ac6/src/tx_timer_interrupt.S | 8 +++++++- .../gnu/example_build/tx_initialize_low_level.S | 8 +++++++- ports/cortex_a17/gnu/src/tx_thread_context_restore.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_context_save.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_schedule.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_stack_build.S | 6 +++--- ports/cortex_a17/gnu/src/tx_thread_system_return.S | 6 +++--- .../cortex_a17/gnu/src/tx_thread_vectored_context_save.S | 6 +++--- ports/cortex_a17/gnu/src/tx_timer_interrupt.S | 6 +++--- ports/cortex_a5/ac6/example_build/tx/.cproject | 4 ++-- ports/cortex_a5/ac6/src/tx_thread_context_restore.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_thread_context_save.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_thread_fiq_context_restore.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_thread_fiq_context_save.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_end.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_start.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_thread_interrupt_control.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_thread_interrupt_disable.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_thread_interrupt_restore.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_thread_irq_nesting_end.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_thread_irq_nesting_start.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_thread_schedule.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_thread_stack_build.S | 9 ++++++++- ports/cortex_a5/ac6/src/tx_thread_system_return.S | 8 +++++++- .../cortex_a5/ac6/src/tx_thread_vectored_context_save.S | 8 +++++++- ports/cortex_a5/ac6/src/tx_timer_interrupt.S | 8 +++++++- .../gnu/example_build/tx_initialize_low_level.S | 8 +++++++- ports/cortex_a5/gnu/src/tx_thread_context_restore.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_context_save.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_schedule.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_stack_build.S | 6 +++--- ports/cortex_a5/gnu/src/tx_thread_system_return.S | 6 +++--- .../cortex_a5/gnu/src/tx_thread_vectored_context_save.S | 6 +++--- ports/cortex_a5/gnu/src/tx_timer_interrupt.S | 6 +++--- ports/cortex_a7/ac6/src/tx_thread_context_restore.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_thread_context_save.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_thread_fiq_context_restore.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_thread_fiq_context_save.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_thread_schedule.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_thread_stack_build.S | 9 ++++++++- ports/cortex_a7/ac6/src/tx_thread_system_return.S | 8 +++++++- .../cortex_a7/ac6/src/tx_thread_vectored_context_save.S | 8 +++++++- ports/cortex_a7/ac6/src/tx_timer_interrupt.S | 8 +++++++- .../gnu/example_build/tx_initialize_low_level.S | 8 +++++++- ports/cortex_a7/gnu/src/tx_thread_context_restore.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_context_save.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_schedule.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_stack_build.S | 6 +++--- ports/cortex_a7/gnu/src/tx_thread_system_return.S | 6 +++--- .../cortex_a7/gnu/src/tx_thread_vectored_context_save.S | 7 ++++--- ports/cortex_a7/gnu/src/tx_timer_interrupt.S | 6 +++--- ports/cortex_a8/ac6/src/tx_thread_context_restore.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_thread_context_save.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_thread_fiq_context_restore.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_thread_fiq_context_save.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_thread_schedule.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_thread_stack_build.S | 9 ++++++++- ports/cortex_a8/ac6/src/tx_thread_system_return.S | 8 +++++++- .../cortex_a8/ac6/src/tx_thread_vectored_context_save.S | 8 +++++++- ports/cortex_a8/ac6/src/tx_timer_interrupt.S | 8 +++++++- .../gnu/example_build/tx_initialize_low_level.S | 8 +++++++- ports/cortex_a8/gnu/src/tx_thread_context_restore.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_context_save.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_schedule.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_stack_build.S | 6 +++--- ports/cortex_a8/gnu/src/tx_thread_system_return.S | 6 +++--- .../cortex_a8/gnu/src/tx_thread_vectored_context_save.S | 6 +++--- ports/cortex_a8/gnu/src/tx_timer_interrupt.S | 6 +++--- ports/cortex_a9/ac6/src/tx_thread_context_restore.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_thread_context_save.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_thread_fiq_context_restore.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_thread_fiq_context_save.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_thread_schedule.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_thread_stack_build.S | 9 ++++++++- ports/cortex_a9/ac6/src/tx_thread_system_return.S | 8 +++++++- .../cortex_a9/ac6/src/tx_thread_vectored_context_save.S | 8 +++++++- ports/cortex_a9/ac6/src/tx_timer_interrupt.S | 8 +++++++- .../gnu/example_build/tx_initialize_low_level.S | 8 +++++++- ports/cortex_a9/gnu/src/tx_thread_context_restore.S | 6 +++--- ports/cortex_a9/gnu/src/tx_thread_context_save.S | 6 +++--- ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S | 6 +++--- ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S | 6 +++--- ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S | 6 +++--- ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S | 6 +++--- ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S | 6 +++--- ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S | 6 +++--- ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S | 6 +++--- ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S | 7 +++---- ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S | 7 +++---- ports/cortex_a9/gnu/src/tx_thread_schedule.S | 7 +++---- ports/cortex_a9/gnu/src/tx_thread_stack_build.S | 6 +++--- ports/cortex_a9/gnu/src/tx_thread_system_return.S | 7 +++---- .../cortex_a9/gnu/src/tx_thread_vectored_context_save.S | 6 +++--- ports/cortex_a9/gnu/src/tx_timer_interrupt.S | 6 +++--- 232 files changed, 1179 insertions(+), 461 deletions(-) diff --git a/ports/cortex_a12/ac6/src/tx_thread_context_restore.S b/ports/cortex_a12/ac6/src/tx_thread_context_restore.S index fae7e72dc..88c15c13f 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a12/ac6/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -50,7 +53,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,6 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a12/ac6/src/tx_thread_context_save.S b/ports/cortex_a12/ac6/src/tx_thread_context_save.S index 7ac48c2ec..e24425bb5 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a12/ac6/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -36,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a12/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a12/ac6/src/tx_thread_fiq_context_restore.S index 006be9732..a0a834fbd 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a12/ac6/src/tx_thread_fiq_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif SVC_MODE = 0xD3 // SVC mode FIQ_MODE = 0xD1 // FIQ mode @@ -48,7 +51,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,6 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a12/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a12/ac6/src/tx_thread_fiq_context_save.S index 7db6a4c2f..57b8d73b2 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a12/ac6/src/tx_thread_fiq_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -37,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S index b34d881ef..f14a39eb4 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -40,7 +43,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,6 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S index c9cd5a069..b4d61ac8f 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask @@ -36,7 +39,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S index 63b1609af..8a3b4edef 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif INT_MASK = 0x03F @@ -47,7 +50,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -80,6 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S index 13258808e..f4b9e31b9 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for applications calling this function from to 16-bit Thumb mode. */ @@ -44,7 +47,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,6 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S index 2d5825112..9bd4cb300 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for applications calling this function from to 16-bit Thumb mode. */ @@ -44,7 +47,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,6 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S index ec7e63c62..8c2f4b92c 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -40,7 +43,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,6 +85,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S index c69976edb..35727b89f 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask @@ -36,7 +39,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a12/ac6/src/tx_thread_schedule.S b/ports/cortex_a12/ac6/src/tx_thread_schedule.S index 8330e9dff..6af94e945 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a12/ac6/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_execute_ptr .global _tx_thread_current_ptr @@ -50,7 +53,7 @@ $_tx_thread_schedule: /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -89,6 +92,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a12/ac6/src/tx_thread_stack_build.S b/ports/cortex_a12/ac6/src/tx_thread_stack_build.S index f413e6739..7aa7c0877 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a12/ac6/src/tx_thread_stack_build.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 // SVC mode @@ -54,7 +58,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -89,6 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a12/ac6/src/tx_thread_system_return.S b/ports/cortex_a12/ac6/src/tx_thread_system_return.S index cb7d62ce1..6e59880dc 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a12/ac6/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -54,7 +57,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -92,6 +95,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a12/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a12/ac6/src/tx_thread_vectored_context_save.S index d846223fc..495e850ae 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a12/ac6/src/tx_thread_vectored_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -37,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_vectored_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a12/ac6/src/tx_timer_interrupt.S b/ports/cortex_a12/ac6/src/tx_timer_interrupt.S index 7337ed0cd..1a4bc73b1 100644 --- a/ports/cortex_a12/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a12/ac6/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -61,7 +64,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,6 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a12/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a12/gnu/example_build/tx_initialize_low_level.S index 7de5d3cea..4b324e0ac 100644 --- a/ports/cortex_a12/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a12/gnu/example_build/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -64,7 +67,7 @@ $_tx_initialize_low_level: /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -100,6 +103,9 @@ $_tx_initialize_low_level: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_initialize_low_level diff --git a/ports/cortex_a12/gnu/src/tx_thread_context_restore.S b/ports/cortex_a12/gnu/src/tx_thread_context_restore.S index 2d6e15661..88c15c13f 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a12/gnu/src/tx_thread_context_restore.S @@ -53,7 +53,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -91,9 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a12/gnu/src/tx_thread_context_save.S b/ports/cortex_a12/gnu/src/tx_thread_context_save.S index 7f88280fd..e24425bb5 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a12/gnu/src/tx_thread_context_save.S @@ -39,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,9 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S index 17ad02bfb..a0a834fbd 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S @@ -51,7 +51,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -89,9 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S index 7ab2ee942..57b8d73b2 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,9 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S index 52282fc96..f14a39eb4 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S @@ -43,7 +43,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -85,9 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S index 3fd8c0013..b4d61ac8f 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S @@ -39,7 +39,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,9 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S index 092e9a313..8a3b4edef 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S @@ -50,7 +50,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,9 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S index f6ff78247..f4b9e31b9 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S @@ -47,7 +47,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,9 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S index 6543798e3..9bd4cb300 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S @@ -47,7 +47,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -80,9 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S index 759421e8b..8c2f4b92c 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S @@ -43,7 +43,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -85,9 +85,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S index a02846e67..35727b89f 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S @@ -39,7 +39,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,9 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a12/gnu/src/tx_thread_schedule.S b/ports/cortex_a12/gnu/src/tx_thread_schedule.S index e36e01edb..6af94e945 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a12/gnu/src/tx_thread_schedule.S @@ -53,7 +53,7 @@ $_tx_thread_schedule: /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -92,9 +92,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a12/gnu/src/tx_thread_stack_build.S b/ports/cortex_a12/gnu/src/tx_thread_stack_build.S index 624670b4f..7aa7c0877 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a12/gnu/src/tx_thread_stack_build.S @@ -58,7 +58,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -93,9 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a12/gnu/src/tx_thread_system_return.S b/ports/cortex_a12/gnu/src/tx_thread_system_return.S index 13475407d..6e59880dc 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a12/gnu/src/tx_thread_system_return.S @@ -57,7 +57,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,9 +95,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a12/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a12/gnu/src/tx_thread_vectored_context_save.S index f9ba7889c..495e850ae 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a12/gnu/src/tx_thread_vectored_context_save.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_vectored_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,9 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a12/gnu/src/tx_timer_interrupt.S b/ports/cortex_a12/gnu/src/tx_timer_interrupt.S index 717d26200..1a4bc73b1 100644 --- a/ports/cortex_a12/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a12/gnu/src/tx_timer_interrupt.S @@ -64,7 +64,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -101,9 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a15/ac6/src/tx_thread_context_restore.S b/ports/cortex_a15/ac6/src/tx_thread_context_restore.S index fae7e72dc..88c15c13f 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a15/ac6/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -50,7 +53,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,6 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a15/ac6/src/tx_thread_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_context_save.S index 7ac48c2ec..e24425bb5 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a15/ac6/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -36,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S index 006be9732..a0a834fbd 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif SVC_MODE = 0xD3 // SVC mode FIQ_MODE = 0xD1 // FIQ mode @@ -48,7 +51,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,6 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S index 7db6a4c2f..57b8d73b2 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -37,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S index b34d881ef..f14a39eb4 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -40,7 +43,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,6 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S index c9cd5a069..b4d61ac8f 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask @@ -36,7 +39,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S index 63b1609af..8a3b4edef 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif INT_MASK = 0x03F @@ -47,7 +50,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -80,6 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S index 13258808e..f4b9e31b9 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for applications calling this function from to 16-bit Thumb mode. */ @@ -44,7 +47,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,6 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S index 2d5825112..9bd4cb300 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for applications calling this function from to 16-bit Thumb mode. */ @@ -44,7 +47,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,6 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S index ec7e63c62..8c2f4b92c 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -40,7 +43,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,6 +85,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S index c69976edb..35727b89f 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask @@ -36,7 +39,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a15/ac6/src/tx_thread_schedule.S b/ports/cortex_a15/ac6/src/tx_thread_schedule.S index 8330e9dff..6af94e945 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a15/ac6/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_execute_ptr .global _tx_thread_current_ptr @@ -50,7 +53,7 @@ $_tx_thread_schedule: /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -89,6 +92,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a15/ac6/src/tx_thread_stack_build.S b/ports/cortex_a15/ac6/src/tx_thread_stack_build.S index f413e6739..7aa7c0877 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a15/ac6/src/tx_thread_stack_build.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 // SVC mode @@ -54,7 +58,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -89,6 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a15/ac6/src/tx_thread_system_return.S b/ports/cortex_a15/ac6/src/tx_thread_system_return.S index cb7d62ce1..6e59880dc 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a15/ac6/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -54,7 +57,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -92,6 +95,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S index d846223fc..495e850ae 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -37,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_vectored_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a15/ac6/src/tx_timer_interrupt.S b/ports/cortex_a15/ac6/src/tx_timer_interrupt.S index 7337ed0cd..1a4bc73b1 100644 --- a/ports/cortex_a15/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a15/ac6/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -61,7 +64,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,6 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a15/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a15/gnu/example_build/tx_initialize_low_level.S index 7de5d3cea..4b324e0ac 100644 --- a/ports/cortex_a15/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a15/gnu/example_build/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -64,7 +67,7 @@ $_tx_initialize_low_level: /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -100,6 +103,9 @@ $_tx_initialize_low_level: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_initialize_low_level diff --git a/ports/cortex_a15/gnu/src/tx_thread_context_restore.S b/ports/cortex_a15/gnu/src/tx_thread_context_restore.S index 2d6e15661..88c15c13f 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_context_restore.S @@ -53,7 +53,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -91,9 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a15/gnu/src/tx_thread_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_context_save.S index 7f88280fd..e24425bb5 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_context_save.S @@ -39,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,9 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S index 17ad02bfb..a0a834fbd 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S @@ -51,7 +51,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -89,9 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S index 7ab2ee942..57b8d73b2 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,9 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S index 52282fc96..f14a39eb4 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S @@ -43,7 +43,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -85,9 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S index 3fd8c0013..b4d61ac8f 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S @@ -39,7 +39,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,9 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S index 092e9a313..8a3b4edef 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S @@ -50,7 +50,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,9 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S index f6ff78247..f4b9e31b9 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S @@ -47,7 +47,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,9 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S index 6543798e3..9bd4cb300 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S @@ -47,7 +47,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -80,9 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S index 759421e8b..8c2f4b92c 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S @@ -43,7 +43,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -85,9 +85,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S index a02846e67..35727b89f 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S @@ -39,7 +39,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,9 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a15/gnu/src/tx_thread_schedule.S b/ports/cortex_a15/gnu/src/tx_thread_schedule.S index e36e01edb..6af94e945 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a15/gnu/src/tx_thread_schedule.S @@ -53,7 +53,7 @@ $_tx_thread_schedule: /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -92,9 +92,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a15/gnu/src/tx_thread_stack_build.S b/ports/cortex_a15/gnu/src/tx_thread_stack_build.S index 624670b4f..7aa7c0877 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a15/gnu/src/tx_thread_stack_build.S @@ -58,7 +58,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -93,9 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a15/gnu/src/tx_thread_system_return.S b/ports/cortex_a15/gnu/src/tx_thread_system_return.S index 13475407d..6e59880dc 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a15/gnu/src/tx_thread_system_return.S @@ -57,7 +57,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,9 +95,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S index f9ba7889c..495e850ae 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_vectored_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,9 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a15/gnu/src/tx_timer_interrupt.S b/ports/cortex_a15/gnu/src/tx_timer_interrupt.S index 717d26200..1a4bc73b1 100644 --- a/ports/cortex_a15/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a15/gnu/src/tx_timer_interrupt.S @@ -64,7 +64,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -101,9 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a17/ac6/src/tx_thread_context_restore.S b/ports/cortex_a17/ac6/src/tx_thread_context_restore.S index fae7e72dc..88c15c13f 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a17/ac6/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -50,7 +53,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,6 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a17/ac6/src/tx_thread_context_save.S b/ports/cortex_a17/ac6/src/tx_thread_context_save.S index 7ac48c2ec..e24425bb5 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a17/ac6/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -36,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a17/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a17/ac6/src/tx_thread_fiq_context_restore.S index 006be9732..a0a834fbd 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a17/ac6/src/tx_thread_fiq_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif SVC_MODE = 0xD3 // SVC mode FIQ_MODE = 0xD1 // FIQ mode @@ -48,7 +51,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,6 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a17/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a17/ac6/src/tx_thread_fiq_context_save.S index 7db6a4c2f..57b8d73b2 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a17/ac6/src/tx_thread_fiq_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -37,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S index b34d881ef..f14a39eb4 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -40,7 +43,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,6 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S index c9cd5a069..b4d61ac8f 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask @@ -36,7 +39,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S index 63b1609af..8a3b4edef 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif INT_MASK = 0x03F @@ -47,7 +50,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -80,6 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S index 13258808e..f4b9e31b9 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for applications calling this function from to 16-bit Thumb mode. */ @@ -44,7 +47,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,6 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S index 2d5825112..9bd4cb300 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for applications calling this function from to 16-bit Thumb mode. */ @@ -44,7 +47,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,6 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S index ec7e63c62..8c2f4b92c 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -40,7 +43,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,6 +85,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S index c69976edb..35727b89f 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask @@ -36,7 +39,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a17/ac6/src/tx_thread_schedule.S b/ports/cortex_a17/ac6/src/tx_thread_schedule.S index 8330e9dff..6af94e945 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a17/ac6/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_execute_ptr .global _tx_thread_current_ptr @@ -50,7 +53,7 @@ $_tx_thread_schedule: /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -89,6 +92,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a17/ac6/src/tx_thread_stack_build.S b/ports/cortex_a17/ac6/src/tx_thread_stack_build.S index f413e6739..7aa7c0877 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a17/ac6/src/tx_thread_stack_build.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 // SVC mode @@ -54,7 +58,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -89,6 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a17/ac6/src/tx_thread_system_return.S b/ports/cortex_a17/ac6/src/tx_thread_system_return.S index cb7d62ce1..6e59880dc 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a17/ac6/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -54,7 +57,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -92,6 +95,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a17/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a17/ac6/src/tx_thread_vectored_context_save.S index d846223fc..495e850ae 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a17/ac6/src/tx_thread_vectored_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -37,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_vectored_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a17/ac6/src/tx_timer_interrupt.S b/ports/cortex_a17/ac6/src/tx_timer_interrupt.S index 7337ed0cd..1a4bc73b1 100644 --- a/ports/cortex_a17/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a17/ac6/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -61,7 +64,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -98,6 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a17/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a17/gnu/example_build/tx_initialize_low_level.S index 7de5d3cea..4b324e0ac 100644 --- a/ports/cortex_a17/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a17/gnu/example_build/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -64,7 +67,7 @@ $_tx_initialize_low_level: /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -100,6 +103,9 @@ $_tx_initialize_low_level: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_initialize_low_level diff --git a/ports/cortex_a17/gnu/src/tx_thread_context_restore.S b/ports/cortex_a17/gnu/src/tx_thread_context_restore.S index 2d6e15661..88c15c13f 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a17/gnu/src/tx_thread_context_restore.S @@ -53,7 +53,7 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -91,9 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a17/gnu/src/tx_thread_context_save.S b/ports/cortex_a17/gnu/src/tx_thread_context_save.S index 7f88280fd..e24425bb5 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a17/gnu/src/tx_thread_context_save.S @@ -39,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,9 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S index 17ad02bfb..a0a834fbd 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S @@ -51,7 +51,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -89,9 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S index 7ab2ee942..57b8d73b2 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,9 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S index 52282fc96..f14a39eb4 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S @@ -43,7 +43,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -85,9 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S index 3fd8c0013..b4d61ac8f 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S @@ -39,7 +39,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,9 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S index 092e9a313..8a3b4edef 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S @@ -50,7 +50,7 @@ $_tx_thread_interrupt_control: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,9 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S index f6ff78247..f4b9e31b9 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S @@ -47,7 +47,7 @@ $_tx_thread_interrupt_disable: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,9 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S index 6543798e3..9bd4cb300 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S @@ -47,7 +47,7 @@ $_tx_thread_interrupt_restore: /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -80,9 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S index 759421e8b..8c2f4b92c 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S @@ -43,7 +43,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -85,9 +85,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S index a02846e67..35727b89f 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S @@ -39,7 +39,7 @@ SYS_MODE_BITS = 0x1F // System mode bits /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,9 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a17/gnu/src/tx_thread_schedule.S b/ports/cortex_a17/gnu/src/tx_thread_schedule.S index e36e01edb..6af94e945 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a17/gnu/src/tx_thread_schedule.S @@ -53,7 +53,7 @@ $_tx_thread_schedule: /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -92,9 +92,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a17/gnu/src/tx_thread_stack_build.S b/ports/cortex_a17/gnu/src/tx_thread_stack_build.S index 624670b4f..7aa7c0877 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a17/gnu/src/tx_thread_stack_build.S @@ -58,7 +58,7 @@ $_tx_thread_stack_build: /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -93,9 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a17/gnu/src/tx_thread_system_return.S b/ports/cortex_a17/gnu/src/tx_thread_system_return.S index 13475407d..6e59880dc 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a17/gnu/src/tx_thread_system_return.S @@ -57,7 +57,7 @@ $_tx_thread_system_return: /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,9 +95,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a17/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a17/gnu/src/tx_thread_vectored_context_save.S index f9ba7889c..495e850ae 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a17/gnu/src/tx_thread_vectored_context_save.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_vectored_context_save ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,9 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a17/gnu/src/tx_timer_interrupt.S b/ports/cortex_a17/gnu/src/tx_timer_interrupt.S index 717d26200..1a4bc73b1 100644 --- a/ports/cortex_a17/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a17/gnu/src/tx_timer_interrupt.S @@ -64,7 +64,7 @@ $_tx_timer_interrupt: /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt ARMv7-A */ -/* 6.1.11 */ +/* 6.x */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -101,9 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* xx-xx-xxxx Tiejun Zhou Modified comment(s), added */ /* #include tx_user.h, */ -/* resulting in version 6.2.1 */ +/* resulting in version 6.x */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a5/ac6/example_build/tx/.cproject b/ports/cortex_a5/ac6/example_build/tx/.cproject index 730528ae0..22e5a64ca 100644 --- a/ports/cortex_a5/ac6/example_build/tx/.cproject +++ b/ports/cortex_a5/ac6/example_build/tx/.cproject @@ -45,7 +45,7 @@