[libcpu][risc-v] Refactor the RISC-V architecture port

Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.

- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration

Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.

Signed-off-by: GuEe-GUI <2991707448@qq.com>

Author: GuEe-GUI

bsp/qemu-virt64-riscv/.config

@@ -1,3 +1,5 @@
-mnt.c
-romfs_data.c
+*.dtb
+*.dts
+*.qcow2
 opensbi
+romfs_data.c

bsp/qemu-virt64-riscv/.gitignore

@@ -6,52 +6,53 @@ RTT_DIR := ../../
 
 PKGS_DIR := packages
 
+SOC_DM_PIC_DIR      := $(RTT_DIR)/libcpu/risc-v/common/pic
+SOC_DM_SERIAL_DIR   := $(RTT_DIR)/libcpu/risc-v/common/serial
+SOC_DM_HWCACHE_DIR  := $(RTT_DIR)/libcpu/risc-v/common/hwcache
+SOC_DM_SOC_DIR      := $(BSP_DIR)/driver
+
+choice
+    prompt "RISC-V XLEN"
+    default BSP_QEMU_RISCV64
+
+    config BSP_QEMU_RISCV32
+        bool "RV32"
+
+    config BSP_QEMU_RISCV64
+        bool "RV64"
+endchoice
+
+config ARCH_TEXT_OFFSET
+    range 0x400000 0x400000 if BSP_QEMU_RISCV32
+    range 0x200000 0x200000 if BSP_QEMU_RISCV64
+    default 0x400000 if BSP_QEMU_RISCV32
+    default 0x200000 if BSP_QEMU_RISCV64
+
+config ARCH_RAM_OFFSET
+    range 0x80000000 0x80000000
+    default 0x80000000
+
 source "$(RTT_DIR)/Kconfig"
 osource "$PKGS_DIR/Kconfig"
-rsource "driver/Kconfig"
 
-config BOARD_QEMU_VIRT_RV64
+config BSP_USING_QEMU_RISCV_VIRT
     bool
-    select ARCH_RISCV64
-    select ARCH_USING_RISCV_COMMON64
+    select ARCH_RISCV
+    select ARCH_CPU_64BIT if BSP_QEMU_RISCV64
+    select RT_USING_RISCV_NEW_COMMON
+    select ARCH_RISCV_USING_GENERIC_STARTUP
+    select ARCH_RISCV_USING_GENERIC_LINKER_SCRIPT
+    select ARCH_RISCV_USING_GENERIC_SETUP
+    select RT_USING_DM
+    select RT_USING_OFW
+    select RT_USING_PIC
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     select RT_USING_CACHE
     select ARCH_MM_MMU
-    select ARCH_REMAP_KERNEL
-    default y
-
-config ENABLE_FPU
-    bool "Enable FPU"
-    select ARCH_RISCV_FPU
+    select ARCH_REMAP_KERNEL if RT_USING_SMART
+    select ARCH_RISCV_FPU_D if BSP_QEMU_RISCV64
+    select ARCH_RISCV_VECTOR if BSP_QEMU_RISCV64
+    select RT_KLIBC_USING_VSNPRINTF_LONGLONG
+    select RT_USING_STDC_ATOMIC
     default y
-
-config ENABLE_VECTOR
-    bool "Using RISC-V Vector Extension"
-    select ARCH_RISCV_VECTOR
-    default n
-
-if ENABLE_VECTOR
-    choice ARCH_VECTOR_VLEN_SEL
-    prompt "Vector Registers Length in Bits"
-    default ARCH_VECTOR_VLEN_128
-
-    config ARCH_VECTOR_VLEN_128
-        bool "128"
-
-    config ARCH_VECTOR_VLEN_256
-        bool "256"
-    endchoice
-endif
-
-config RT_USING_USERSPACE_32BIT_LIMIT
-    bool "Enable userspace 32bit limit"
-    default n
-
-config RT_USING_VIRTIO_MMIO_ALIGN
-    bool "Open packed attribution, this may caused an error on virtio"
-    default n
-
-config __STACKSIZE__
-    int "stack size for interrupt"
-    default 4096