core_arch: redefine svtrn{1,2}

Same as previous redefinitions in stdarch#2163 - these were missed in
that PR because the hardware being tested on was missing the hardware
feature required for the instructions these use.

Author: davidtwco

library/stdarch/crates/core_arch/src/aarch64/sve/generated.rs

@@ -42211,30 +42211,17 @@ pub fn svtmad_f64<const IMM3: i32>(op1: svfloat64_t, op2: svfloat64_t) -> svfloa
     unsafe { _svtmad_f64(op1, op2, IMM3) }
 }
 #[doc = "Interleave even elements from two inputs"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b8)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(trn1))]
-pub fn svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv16i1")]
-        fn _svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
-    }
-    unsafe { _svtrn1_b8(op1, op2) }
-}
-#[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b16)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
 pub fn svtrn1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv8i1")]
-        fn _svtrn1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.b16")]
+        fn _svtrn1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svtrn1_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svtrn1_b16(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b32)"]
@@ -42244,10 +42231,10 @@ pub fn svtrn1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(trn1))]
 pub fn svtrn1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4i1")]
-        fn _svtrn1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.b32")]
+        fn _svtrn1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svtrn1_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svtrn1_b32(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b64)"]
@@ -42257,10 +42244,10 @@ pub fn svtrn1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(trn1))]
 pub fn svtrn1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2i1")]
-        fn _svtrn1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.b64")]
+        fn _svtrn1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svtrn1_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svtrn1_b64(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_f32])"]
@@ -42376,6 +42363,19 @@ pub fn svtrn1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 pub fn svtrn1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
     unsafe { svtrn1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
 }
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_b8])"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv16i1")]
+        fn _svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svtrn1_b8(op1, op2) }
+}
 #[doc = "Interleave even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_f32])"]
 #[inline]
@@ -42491,30 +42491,17 @@ pub fn svtrn1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
     unsafe { svtrn1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
 }
 #[doc = "Interleave odd elements from two inputs"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b8)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(trn2))]
-pub fn svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv16i1")]
-        fn _svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
-    }
-    unsafe { _svtrn2_b8(op1, op2) }
-}
-#[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b16)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
 pub fn svtrn2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv8i1")]
-        fn _svtrn2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.b16")]
+        fn _svtrn2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svtrn2_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svtrn2_b16(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b32)"]
@@ -42524,10 +42511,10 @@ pub fn svtrn2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(trn2))]
 pub fn svtrn2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4i1")]
-        fn _svtrn2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.b32")]
+        fn _svtrn2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svtrn2_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svtrn2_b32(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b64)"]
@@ -42537,10 +42524,10 @@ pub fn svtrn2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(trn2))]
 pub fn svtrn2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2i1")]
-        fn _svtrn2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.b64")]
+        fn _svtrn2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svtrn2_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svtrn2_b64(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_f32])"]
@@ -42656,6 +42643,19 @@ pub fn svtrn2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 pub fn svtrn2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
     unsafe { svtrn2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
 }
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_b8])"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv16i1")]
+        fn _svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svtrn2_b8(op1, op2) }
+}
 #[doc = "Interleave odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_f32])"]
 #[inline]

library/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml

@@ -1157,7 +1157,7 @@ intrinsics:
     doc: Interleave even elements from two inputs
     arguments: ["op1: {sve_type}", "op2: {sve_type}"]
     return_type: "{sve_type}"
-    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
     assert_instr: [trn1]
     compose:
       - LLVMLink: { name: "trn1.{sve_type}" }
@@ -1167,10 +1167,13 @@ intrinsics:
     doc: Interleave even elements from two inputs
     arguments: ["op1: {sve_type}", "op2: {sve_type}"]
     return_type: "{sve_type}"
-    types: [b8, b16, b32, b64]
+    types: [b16, b32, b64]
     assert_instr: [trn1]
     compose:
-      - LLVMLink: { name: "trn1.{sve_type}" }
+      - LLVMLink:
+          name: "llvm.aarch64.sve.trn1.b{size}"
+          arguments: ["op1: svbool_t", "op2: svbool_t"]
+          return_type: "svbool_t"
 
   - name: svtrn1q[_{type}]
     attr: [*sve-unstable]
@@ -1188,7 +1191,7 @@ intrinsics:
     doc: Interleave odd elements from two inputs
     arguments: ["op1: {sve_type}", "op2: {sve_type}"]
     return_type: "{sve_type}"
-    types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
+    types: [b8, f32, f64, i8, i16, i32, i64, u8, u16, u32, u64]
     assert_instr: [trn2]
     compose:
       - LLVMLink: { name: "trn2.{sve_type}" }
@@ -1198,10 +1201,13 @@ intrinsics:
     doc: Interleave odd elements from two inputs
     arguments: ["op1: {sve_type}", "op2: {sve_type}"]
     return_type: "{sve_type}"
-    types: [b8, b16, b32, b64]
+    types: [b16, b32, b64]
     assert_instr: [trn2]
     compose:
-      - LLVMLink: { name: "trn2.{sve_type}" }
+      - LLVMLink:
+          name: "llvm.aarch64.sve.trn2.b{size}"
+          arguments: ["op1: svbool_t", "op2: svbool_t"]
+          return_type: "svbool_t"
 
   - name: svtrn2q[_{type}]
     attr: [*sve-unstable]