Move add to v15 on arm

Author: AntoinePrv

include/xsimd/arch/utils/sve.hpp

@@ -0,0 +1,51 @@
+/****************************************************************************
+ * Copyright (c) xsimd contributors                                         *
+ *                                                                          *
+ * Distributed under the terms of the BSD 3-Clause License.                 *
+ *                                                                          *
+ * The full license is in the file LICENSE, distributed with this software. *
+ ****************************************************************************/
+
+#ifndef XSIMD_ARCH_UTILS_SVE_HPP
+#define XSIMD_ARCH_UTILS_SVE_HPP
+
+#include "../../config/xsimd_macros.hpp"
+#include "../../types/xsimd_sve_register.hpp"
+
+#include <type_traits>
+
+// Define a inline namespace with the explicit SVE vector size to avoid ODR violation
+// When dynamically dispatching between different SVE sizes.
+// While most code is safe from ODR violation as the size is already encoded in the
+// register (and hence batch) types, utilities can quickly fall prone to this issue.
+#define XSIMD_SVE_NAMESPACE XSIMD_CONCAT(sve, XSIMD_SVE_BITS)
+
+namespace xsimd::kernel::detail
+{
+    inline namespace XSIMD_SVE_NAMESPACE
+    {
+        template <class T>
+        XSIMD_INLINE auto svptrue() noexcept
+        {
+#if XSIMD_WITH_SVE
+            if constexpr (sizeof(T) == 1)
+            {
+                return svptrue_b8();
+            }
+            else if constexpr (sizeof(T) == 2)
+            {
+                return svptrue_b16();
+            }
+            else if constexpr (sizeof(T) == 4)
+            {
+                return svptrue_b32();
+            }
+            else if constexpr (sizeof(T) == 8)
+            {
+                return svptrue_b64();
+            }
+#endif
+        }
+    }
+}
+#endif

include/xsimd/arch/xsimd_isa.hpp

@@ -16,6 +16,11 @@
 #include "../config/xsimd_arch.hpp"
 #include "./xsimd_common_fwd.hpp"
 
+// v15 API under migration
+#if XSIMD_WITH_NEON || XSIMD_WITH_SVE
+#include "../v15/arithmetic/arm.hpp"
+#endif
+
 #if XSIMD_WITH_EMULATED
 #include "./xsimd_emulated.hpp"
 #endif

include/xsimd/arch/xsimd_neon.hpp

@@ -811,42 +811,6 @@ namespace xsimd
             return vnegq_f32(rhs);
         }
 
-        /*******
-         * add *
-         *******/
-
-        namespace wrap
-        {
-            // TODO(c++17): Make a single function with if constexpr  switch
-            // Templating on the scalar type `T` is required because in some compilers (e.g. MSVC)
-            // the vector types are all aliases of the same type.
-            template <class T, std::enable_if_t<std::is_same_v<T, uint8_t>, int> = 0>
-            XSIMD_INLINE uint8x16_t x_vaddq(uint8x16_t a, uint8x16_t b) noexcept { return vaddq_u8(a, b); }
-            template <class T, std::enable_if_t<std::is_same_v<T, int8_t>, int> = 0>
-            XSIMD_INLINE int8x16_t x_vaddq(int8x16_t a, int8x16_t b) noexcept { return vaddq_s8(a, b); }
-            template <class T, std::enable_if_t<std::is_same_v<T, uint16_t>, int> = 0>
-            XSIMD_INLINE uint16x8_t x_vaddq(uint16x8_t a, uint16x8_t b) noexcept { return vaddq_u16(a, b); }
-            template <class T, std::enable_if_t<std::is_same_v<T, int16_t>, int> = 0>
-            XSIMD_INLINE int16x8_t x_vaddq(int16x8_t a, int16x8_t b) noexcept { return vaddq_s16(a, b); }
-            template <class T, std::enable_if_t<std::is_same_v<T, uint32_t>, int> = 0>
-            XSIMD_INLINE uint32x4_t x_vaddq(uint32x4_t a, uint32x4_t b) noexcept { return vaddq_u32(a, b); }
-            template <class T, std::enable_if_t<std::is_same_v<T, int32_t>, int> = 0>
-            XSIMD_INLINE int32x4_t x_vaddq(int32x4_t a, int32x4_t b) noexcept { return vaddq_s32(a, b); }
-            template <class T, std::enable_if_t<std::is_same_v<T, uint64_t>, int> = 0>
-            XSIMD_INLINE uint64x2_t x_vaddq(uint64x2_t a, uint64x2_t b) noexcept { return vaddq_u64(a, b); }
-            template <class T, std::enable_if_t<std::is_same_v<T, int64_t>, int> = 0>
-            XSIMD_INLINE int64x2_t x_vaddq(int64x2_t a, int64x2_t b) noexcept { return vaddq_s64(a, b); }
-            template <class T, std::enable_if_t<std::is_same_v<T, float>, int> = 0>
-            XSIMD_INLINE float32x4_t x_vaddq(float32x4_t a, float32x4_t b) noexcept { return vaddq_f32(a, b); }
-        }
-
-        template <class A, class T, detail::enable_neon_type_t<T> = 0>
-        XSIMD_INLINE batch<T, A> add(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<neon>) noexcept
-        {
-            using register_type = typename batch<T, A>::register_type;
-            return wrap::x_vaddq<map_to_sized_type_t<T>>(register_type(lhs), register_type(rhs));
-        }
-
         /*******
          * avg *
          *******/

include/xsimd/arch/xsimd_neon64.hpp

@@ -14,6 +14,7 @@
 
 #include "../types/xsimd_neon64_register.hpp"
 #include "../types/xsimd_utils.hpp"
+#include "../v15/kernel_fwd.hpp"
 #include "./xsimd_neon.hpp"
 
 #include <cassert>
@@ -352,24 +353,14 @@ namespace xsimd
             return vnegq_f64(rhs);
         }
 
-        /*******
-         * add *
-         *******/
-
-        template <class A>
-        XSIMD_INLINE batch<double, A> add(batch<double, A> const& lhs, batch<double, A> const& rhs, requires_arch<neon64>) noexcept
-        {
-            return vaddq_f64(lhs, rhs);
-        }
-
         /********
          * sadd *
          ********/
 
         template <class A>
         XSIMD_INLINE batch<double, A> sadd(batch<double, A> const& lhs, batch<double, A> const& rhs, requires_arch<neon64>) noexcept
         {
-            return add(lhs, rhs, neon64 {});
+            return ::xsimd::kernel::add(lhs, rhs);
         }
 
         /*******