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Commit cc21199

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dgarskedgarske
committed
Progress with T2080 port refresh
1 parent a90d60f commit cc21199

4 files changed

Lines changed: 105 additions & 41 deletions

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‎hal/nxp_ppc.h‎

Lines changed: 13 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -118,16 +118,17 @@
118118
#define ENABLE_L1_CACHE
119119
#define ENABLE_L2_CACHE
120120

121-
#define L2SRAM_ADDR (0xF8F00000UL) /* CPC as SRAM (1MB) */
122-
#define L2SRAM_SIZE (1024UL * 1024UL)
121+
/* T2080 CPC SRAM config - 512KB per T2080RM */
122+
#define L2SRAM_ADDR (0xF8F80000UL) /* CPC as SRAM (512KB) */
123+
#define L2SRAM_SIZE (512UL * 1024UL)
123124

124125
#define INITIAL_SRAM_ADDR L2SRAM_ADDR
125126
/* CPC SRAM transactions traverse the CoreNet interconnect, which
126-
* requires a LAW to route them. LAW_TRGT_DDR_1 is used as a routing
127-
* target; the CPC intercepts the transaction before it reaches DDR. */
128-
#define INITIAL_SRAM_LAW_SZ LAW_SIZE_1MB
127+
* requires a LAW to route them. LAW_TRGT_DDR_1 (0x10) is the CPC
128+
* target per T2080RM Table 2-2 (Target ID Assignments). */
129+
#define INITIAL_SRAM_LAW_SZ LAW_SIZE_512KB
129130
#define INITIAL_SRAM_LAW_TRGT LAW_TRGT_DDR_1
130-
#define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_1M
131+
#define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_512K
131132

132133
#define ENABLE_INTERRUPTS
133134

@@ -303,6 +304,7 @@
303304
#ifdef CORE_E6500
304305
/* T2080: 2MB CPC, 16 ways, 128KB per way */
305306
#define CPCSRCR0_SRAMSZ_256 (0x1 << 1) /* ways 14-15, 256KB */
307+
#define CPCSRCR0_SRAMSZ_512 (0x2 << 1) /* ways 12-15, 512KB */
306308
#define CPCSRCR0_SRAMSZ_1024 (0x3 << 1) /* ways 8-15, 1MB */
307309
#define CPCSRCR0_SRAMSZ_2048 (0x4 << 1) /* ways 0-15, 2MB */
308310
#else /* CORE E5500 */
@@ -691,12 +693,12 @@ extern void dcache_disable(void);
691693
#else
692694
/* Assembly version */
693695
#ifdef CORE_E6500
694-
/* e6500 has 64-bit MAS registers - must clear upper 32 bits.
695-
* Using lis would sign-extend values with bit 15 set (e.g., 0xC000xxxx).
696-
* Use li 0; oris; ori pattern for all MAS registers. */
696+
/* e6500 has 64-bit MAS registers. On 64-bit PPC, lis sign-extends to 64 bits.
697+
* Any MAS value with bit 31 set (MAS1=0xC..., MAS2/MAS3 high addresses) gets
698+
* upper 32 bits = 0xFFFFFFFF. Hardware may require reserved upper bits = 0.
699+
* Use "li 0; oris; ori" pattern for MAS1, MAS2, MAS3 to avoid sign-extension. */
697700
#define set_tlb(tlb, esel, epn, rpn, urpn, perms, winge, ts, tsize, iprot, reg) \
698-
li reg, 0; \
699-
oris reg, reg, BOOKE_MAS0(tlb, esel, 0)@h; \
701+
lis reg, BOOKE_MAS0(tlb, esel, 0)@h; \
700702
ori reg, reg, BOOKE_MAS0(tlb, esel, 0)@l; \
701703
mtspr MAS0, reg;\
702704
li reg, 0; \

‎hal/nxp_t2080.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -221,7 +221,7 @@ static void hal_flash_init(void)
221221
#endif /* ENABLE_IFC */
222222
}
223223

224-
static void hal_ddr_init(void)
224+
void hal_ddr_init(void)
225225
{
226226
#ifdef ENABLE_DDR
227227
uint32_t reg;

‎hal/nxp_t2080.ld‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@ MEMORY
1313
{
1414
FLASH (rx) : ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@
1515

16-
/* CPC as SRAM - 1MB */
17-
RAM (rwx) : ORIGIN = 0xF8F00000, LENGTH = 0x100000
16+
/* CPC as SRAM - 512KB (T2080 supports up to 2MB, using 512KB) */
17+
RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x80000
1818

1919
/* DDR - 2GB */
2020
DRAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x7FFFFFFF

‎src/boot_ppc_start.S‎

Lines changed: 89 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -560,6 +560,50 @@ flash_tlb:
560560
#endif
561561
#endif /* ENABLE_DDR */
562562

563+
/* =========================================================================
564+
* CPC SRAM Initialization
565+
* Order: 1) CPC invalidate, 2) CPCSRCR config, 3) LAW, 4) TLB, 5) CPC enable
566+
* Note: TLB must be created BEFORE CPC enable (original working sequence)
567+
* ========================================================================= */
568+
#if defined(ENABLE_L2_CACHE) && defined(L2SRAM_ADDR) && (defined(CORE_E5500) || defined(CORE_E6500))
569+
cpc_setup_sram:
570+
/* T2080RM: 8.4.2.2 - CPC initialization sequence:
571+
* Step 1: Flash invalidate CPC and clear locks (CPCFI | CPCLFC)
572+
* Step 2: Poll until invalidate completes
573+
* Step 3: Configure SRAM control registers (CPCSRCR1, CPCSRCR0)
574+
* Step 4: Configure LAW for SRAM routing (done after this block)
575+
* Step 5: Enable CPC with parity (CPCE | CPCPE)
576+
* Step 6: Create TLB for SRAM access
577+
* The LAW (DDR_1) provides CoreNet routing; CPC intercepts before DDR. */
578+
579+
/* R1 = CPC base - preserve across LAW setup */
580+
LOAD_ADDR32(r1, CPC_BASE)
581+
582+
/* Step 1: Flash invalidate CPC and clear all locks */
583+
lis r0, (CPCCSR0_CPCFI | CPCCSR0_CPCLFC)@h
584+
ori r0, r0, (CPCCSR0_CPCFI | CPCCSR0_CPCLFC)@l
585+
stw r0, CPCCSR0(r1)
586+
587+
/* Step 2: Poll until CPCFI and CPCLFC clear */
588+
cpc_poll_invalidate:
589+
lwz r2, CPCCSR0(r1)
590+
and. r2, r2, r0
591+
bne cpc_poll_invalidate
592+
isync
593+
594+
/* Step 3: Configure CPC SRAM control registers */
595+
li r0, 0
596+
stw r0, CPCSRCR1(r1) /* SRAM high address = 0 */
597+
/* SRAM low address - use LOAD_ADDR32 on e6500 to avoid sign extension */
598+
LOAD_ADDR32(r0, L2SRAM_ADDR)
599+
/* Enable SRAM and set size (must match L2SRAM_SIZE = 512KB) */
600+
ori r0, r0, (CPCSRCR0_SRAMSZ_512 | CPCSRCR0_SRAMEN)
601+
stw r0, CPCSRCR0(r1)
602+
mbar
603+
isync
604+
#endif /* ENABLE_L2_CACHE && L2SRAM_ADDR */
605+
606+
/* Step 3: Configure LAW for SRAM */
563607
#ifdef INITIAL_SRAM_ADDR
564608
#ifndef INITIAL_SRAM_NO_LAW
565609
init_sram_law:
@@ -570,60 +614,60 @@ init_sram_law:
570614
LOAD_ADDR32(r9, CCSRBAR + LAWBAR_BASE(2))
571615
li r0, 0 /* UPPER=0 */
572616
/* Use LOAD_ADDR32 on e6500 to avoid sign-extension for addresses >= 0x80000000 */
573-
LOAD_ADDR32(r1, INITIAL_SRAM_ADDR)
617+
LOAD_ADDR32(r3, INITIAL_SRAM_ADDR)
574618
LOAD_ADDR32(r2, INITIAL_SRAM_LAW)
575619
stw r0, 0(r9) /* LAWBARH */
576-
stw r1, 4(r9) /* LAWBARL */
620+
stw r3, 4(r9) /* LAWBARL */
577621
sync
578622
stw r2, 8(r9) /* LAWAR */
579623
/* read back LAWAR (per 2.3.2 Configuring Local Access Windows) */
580624
lwz r2, 8(r9)
581625
isync
582626
#endif /* !INITIAL_SRAM_NO_LAW */
627+
#endif /* INITIAL_SRAM_ADDR */
583628

629+
/* Step 4: Create TLB for SRAM - BEFORE CPC enable (original working order) */
630+
#ifdef INITIAL_SRAM_ADDR
584631
init_sram_tlb:
585632
/* Initial SRAM: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, IPROT
586-
* CPC SRAM uses cacheable memory-coherent (M) access.
587-
* TLB is created BEFORE l2_setup_sram per old working code. */
633+
* Original working T2080 code (commit 11f46a51) used MAS2_M. */
588634
set_tlb(1, 9,
589635
INITIAL_SRAM_ADDR, INITIAL_SRAM_ADDR, 0,
590636
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0,
591637
INITIAL_SRAM_BOOKE_SZ, 1, r3);
592-
#endif
638+
#endif /* INITIAL_SRAM_ADDR */
593639

594-
#ifdef ENABLE_L2_CACHE
595-
596-
#if defined(CORE_E5500) || defined(CORE_E6500) /* --- L2 E5500/E6500 --- */
597-
#ifdef L2SRAM_ADDR
598-
l2_setup_sram:
599-
/* T2080RM: 8.4.2.2 - CPC initialization
600-
* Configure SRAM control registers, then enable CPC with parity.
601-
* The LAW (DDR_1) provides CoreNet routing; CPC intercepts before DDR.
602-
* SRAM is zeroed later via dcbz through cacheable TLB (MAS2_M). */
640+
/* Step 5: Enable CPC after TLB is configured */
641+
#if defined(ENABLE_L2_CACHE) && defined(L2SRAM_ADDR) && (defined(CORE_E5500) || defined(CORE_E6500))
642+
cpc_enable:
603643
/* R1 = CPC base */
604644
LOAD_ADDR32(r1, CPC_BASE)
605645

606-
/* Configure CPC SRAM control registers */
607-
li r0, 0
608-
stw r0, CPCSRCR1(r1) /* SRAM high address = 0 */
609-
/* SRAM low address - use LOAD_ADDR32 on e6500 to avoid sign extension */
610-
LOAD_ADDR32(r0, L2SRAM_ADDR)
611-
/* Enable SRAM and set size (must match L2SRAM_SIZE) */
612-
ori r0, r0, (CPCSRCR0_SRAMSZ_1024 | CPCSRCR0_SRAMEN)
613-
stw r0, CPCSRCR0(r1)
614-
615646
/* Enable CPC with parity */
616647
lis r0, (CPCCSR0_CPCE | CPCCSR0_CPCPE)@h
617648
mbar
618649
isync
619650
stw r0, CPCCSR0(r1)
620651
mbar
621652

653+
/* Verify CPC is enabled by reading back CPCCSR0 */
654+
cpc_poll_enable:
655+
lwz r2, CPCCSR0(r1)
656+
andis. r2, r2, CPCCSR0_CPCE@h /* check CPCE bit */
657+
beq cpc_poll_enable
658+
isync
659+
622660
/* Disable speculation (Errata A-006593) */
623661
lwz r0, CPCHDBCR0(r1)
624662
oris r0, r0, CPCHDBCR0_SPEC_DIS@h
625663
stw r0, CPCHDBCR0(r1)
626-
#endif /* L2SRAM_ADDR */
664+
mbar
665+
isync
666+
#endif /* ENABLE_L2_CACHE && L2SRAM_ADDR */
667+
668+
#ifdef ENABLE_L2_CACHE
669+
#if defined(CORE_E5500) || defined(CORE_E6500) /* --- L2 E5500/E6500 --- */
670+
/* Note: CPC SRAM setup moved above for correct T2080RM sequence */
627671

628672
#if defined(CORE_E6500) /* --- L2 E6500 --- */
629673
l2_setup_cache:
@@ -653,6 +697,13 @@ l2_poll_invclear:
653697
isync
654698
LOAD_ADDR32(r4, (L2CSR0_L2E | L2CSR0_L2PE))
655699
stw r4, L2CSR0(r5)
700+
mbar
701+
702+
/* Verify L2 is enabled by reading back L2CSR0 */
703+
l2_poll_enable:
704+
lwz r3, L2CSR0(r5)
705+
andis. r3, r3, L2CSR0_L2E@h /* check bit 31 (L2E) */
706+
beq l2_poll_enable /* loop until enabled */
656707
isync
657708

658709
#elif defined(CORE_E5500) /* --- L2 E5500 --- */
@@ -714,6 +765,17 @@ l2_setup_sram:
714765
stw r1, L2SRBAR0(r5)
715766
mbar
716767
#endif /* L2SRAM_ADDR */
768+
769+
#ifdef INITIAL_SRAM_ADDR
770+
init_sram_tlb:
771+
/* Initial SRAM: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, IPROT
772+
* For e500, L2 SRAM uses cacheable memory-coherent (M) access.
773+
* TLB is created AFTER l2_setup_sram configures L2 as SRAM. */
774+
set_tlb(1, 9,
775+
INITIAL_SRAM_ADDR, INITIAL_SRAM_ADDR, 0,
776+
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0,
777+
INITIAL_SRAM_BOOKE_SZ, 1, r3);
778+
#endif /* INITIAL_SRAM_ADDR */
717779
#endif /* CORE_E500 */
718780
#endif /* ENABLE_L2_CACHE */
719781

@@ -776,9 +838,9 @@ cache_sram_init_loop:
776838
bdnz cache_sram_init_loop
777839
#elif defined(L2SRAM_ADDR)
778840
cache_sram_init:
779-
/* Zero CPC SRAM via cache (MAS2_M = cacheable, memory coherent).
780-
* dcbz allocates zeroed cache lines without reading from CPC,
781-
* avoiding ECC/parity issues from uninitialized SRAM. */
841+
/* Zero CPC SRAM via dcbz.
842+
* With MAS2_M (memory-coherent), dcbz allocates zeroed cache lines.
843+
* This initializes SRAM and avoids ECC/parity issues from uninitialized data. */
782844
LOAD_ADDR32(r3, L2SRAM_ADDR)
783845
li r0, 0
784846
LOAD_ADDR32(r2, (L2SRAM_SIZE / CACHE_LINE_SIZE))

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