Restore Agilex 5 SDHCI host reset to match hardware-proven behavior

Author: aidangarske

arch.mk

@@ -175,9 +175,8 @@ ifeq ($(ARCH),AARCH64)
     CFLAGS+=-DWOLFBOOT_DUALBOOT -DWOLFBOOT_UBOOT_LEGACY
     # BL31 owns GICv3 and secondary-core/PSCI setup. Do not touch RVBAR.
     CFLAGS+=-DSKIP_RVBAR=1 -DSKIP_GIC_INIT=1
-    # SPL/TF-A leave the Cadence host initialized; retain its PHY state and
-    # allow the controller's required post-command settle time.
-    CFLAGS_EXTRA+=-DSDHCI_SKIP_HOST_RESET=1 -DSDHCI_WAIT_AFTER_CMD_US=1000
+    # Full SDHCI host reset: SPL leaves the Cadence host in UHS-I 1.8V/SDR104,
+    # which mutes CMD8 against the 3.3V re-powered card (hardware-verified).
   endif
 
   ifeq ($(TARGET),nxp_ls1028a)

hal/agilex5.c

@@ -301,9 +301,8 @@ void sdhci_reg_write(uint32_t offset, uint32_t value)
 
 void sdhci_platform_init(void)
 {
-    /* SPL initialized the host, clocks, reset and pinmux while loading BL31
-     * and BL33. Preserve that live host state and restore the 013B PHY timing
-     * required after wolfBoot takes ownership from TF-A. */
+    /* SPL initialized the clocks and pinmux; the generic driver then soft
+     * resets the host, so restore the 013B PHY timing here. */
     if (agilex5_sdhci_phy_init() != 0)
         wolfBoot_printf("SDHCI: Cadence PHY initialization timed out\n");
 }