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Fixes for QSPI to make sure its properly reset before use
1 parent e0234b6 commit 620266c

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hal/zynq.c

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1359,6 +1359,36 @@ static int qspi_exit_4byte_addr(QspiDev_t* dev)
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}
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#endif
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/* Soft-reset the flash to a known idle state.
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* FSBL / BootROM may leave the flash in an unexpected mode (XIP enabled,
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* 4-byte addr set, auto-boot probing, etc.). Issue RESET_ENABLE (0x66) +
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* RESET_MEMORY (0x99) to bring it back to defaults before first transaction.
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* Per Micron MT25Q datasheet: t_SHSL2 ~ 40 us max after RESET_MEMORY. */
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static int qspi_flash_reset(QspiDev_t* dev)
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{
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int ret;
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uint8_t cmd[4]; /* size multiple of uint32_t */
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memset(cmd, 0, sizeof(cmd));
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cmd[0] = RESET_ENABLE_CMD;
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ret = qspi_transfer(dev, cmd, 1, NULL, 0, NULL, 0, 0,
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GQSPI_GEN_FIFO_MODE_SPI);
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#if defined(DEBUG_ZYNQ) && DEBUG_ZYNQ >= 2
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wolfBoot_printf("Flash Reset Enable: Ret %d\n", ret);
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#endif
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if (ret == GQSPI_CODE_SUCCESS) {
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cmd[0] = RESET_MEMORY_CMD;
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ret = qspi_transfer(dev, cmd, 1, NULL, 0, NULL, 0, 0,
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GQSPI_GEN_FIFO_MODE_SPI);
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#if defined(DEBUG_ZYNQ) && DEBUG_ZYNQ >= 2
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wolfBoot_printf("Flash Reset Memory: Ret %d\n", ret);
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#endif
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}
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/* Allow flash time to complete the reset and become ready. */
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hal_delay_ms(1);
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return ret;
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}
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/* QSPI functions */
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void qspi_init(void)
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{
@@ -1499,6 +1529,19 @@ void qspi_init(void)
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(void)reg_cfg;
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(void)reg_isr;
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/* Issue flash soft reset so we start from a known state regardless of
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* whatever mode FSBL/BootROM left the device in. Send to each chip in
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* dual-parallel configurations by targeting both chip selects. */
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mDev.mode = GQSPI_GEN_FIFO_MODE_SPI;
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mDev.bus = GQSPI_GEN_FIFO_BUS_LOW;
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mDev.cs = GQSPI_GEN_FIFO_CS_LOWER;
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(void)qspi_flash_reset(&mDev);
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#if GQPI_USE_DUAL_PARALLEL == 1
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mDev.bus = GQSPI_GEN_FIFO_BUS_UP;
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mDev.cs = GQSPI_GEN_FIFO_CS_UPPER;
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(void)qspi_flash_reset(&mDev);
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#endif
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/* ------ Flash Read ID (retry) ------ */
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timeout = 0;
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while (++timeout < QSPI_FLASH_READY_TRIES) {

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