Progress testing

Author: dgarske

config/examples/nxp-t1040.config

@@ -26,34 +26,34 @@ WOLFTPM?=0
 ELF?=1
 DEBUG_ELF=0
 
-# NOR Base Address (256MB NOR at 0xE8000000 - 0xF7FFFFFF)
+# NOR Base Address (128MB NOR at 0xE8000000 - 0xEFFFFFFF)
 ARCH_FLASH_OFFSET?=0xE8000000
 
 # Flash Sector Size (128KB)
 WOLFBOOT_SECTOR_SIZE=0x20000
 
-# wolfBoot start address
-WOLFBOOT_ORIGIN=0xF7F40000
+# wolfBoot start address (same as T1024 - NOR top is 0xEFFFFFFF)
+WOLFBOOT_ORIGIN=0xEFF40000
 # wolfBoot partition size (custom)
 BOOTLOADER_PARTITION_SIZE=0xC0000
 
 # Application Partition Size (15MB)
 WOLFBOOT_PARTITION_SIZE?=0xF00000
 # Location in Flash for Application Partition
-WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xF6000000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEE000000
 # Load Partition to RAM Address
 WOLFBOOT_LOAD_ADDRESS?=0x70000000
 
 # Location in Flash for Update Partition
-WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xF6F00000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEEF00000
 
 # Location of temporary sector used during updates
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xE80F0000
 
 # Stage 1 loader settings (16KB)
 WOLFBOOT_STAGE1_SIZE=0x4000
 # Location in Flash for stage 1 loader (XIP from boot ROM)
-WOLFBOOT_STAGE1_FLASH_ADDR=0xF7FFC000
+WOLFBOOT_STAGE1_FLASH_ADDR=0xEFFFC000
 # Address in RAM to load wolfBoot (end of DDR at 2GB-1MB for 32-bit addressing)
 WOLFBOOT_STAGE1_LOAD_ADDR=0x7FF00000
 

docs/Targets.md

@@ -3277,9 +3277,9 @@ Reset Configuration Word (RCW):
 00000020: 00000000 00000000 00000000 00030810
 00000030: 00000000 0342580f 00000000 00000000
 
-Flash is NOR on IFC CS0 (0x0_E800_0000) 256MB.
+Flash is NOR on IFC CS0 (0x0_E800_0000) 128MB (Micron JS28F00AM29EWHA, 16-bit, AMD CFI).
 
-Default NOR Flash Memory Layout (256MB) (128KB block, 1K page)
+Default NOR Flash Memory Layout (128MB) (128KB block, 1K page)
 
 | Description       | Address    | Size                 |
 | ----------------- | ---------- | -------------------- |
@@ -3289,13 +3289,13 @@ Default NOR Flash Memory Layout (256MB) (128KB block, 1K page)
 | Free              | 0xE8100000 | 0x00700000 (  7 MB)  |
 | FDT (Primary)     | 0xE8800000 | 0x00020000 (128 KB)  |
 | FDT (Update)      | 0xE8820000 | 0x00020000 (128 KB)  |
-| Free              | 0xE8840000 | 0x0D7C0000 (~200 MB) |
-| Application (OS)  | 0xF6000000 | 0x00F00000 ( 15 MB)  |
-| Update (OS)       | 0xF6F00000 | 0x00F00000 ( 15 MB)  |
-| QUICC             | 0xF7E00000 | 0x00100000 (  1 MB)  |
-| DPAA (FMAN)       | 0xF7F00000 | 0x00020000 (128 KB)  |
-| wolfBoot          | 0xF7F40000 | 0x000BC000 (752 KB)  |
-| wolfBoot Stage 1  | 0xF7FFC000 | 0x00004000 ( 16 KB)  |
+| Free              | 0xE8840000 | 0x057C0000 ( 87 MB)  |
+| Application (OS)  | 0xEE000000 | 0x00F00000 ( 15 MB)  |
+| Update (OS)       | 0xEEF00000 | 0x00F00000 ( 15 MB)  |
+| QUICC             | 0xEFE00000 | 0x00100000 (  1 MB)  |
+| DPAA (FMAN)       | 0xEFF00000 | 0x00020000 (128 KB)  |
+| wolfBoot          | 0xEFF40000 | 0x000BC000 (752 KB)  |
+| wolfBoot Stage 1  | 0xEFFFC000 | 0x00004000 ( 16 KB)  |
 
 QE: uploading microcode 'Microcode for T1040 r1.0' version 0.0.1
 
@@ -3336,11 +3336,11 @@ If getting errors with keystore then you can reset things using `make distclean`
 ./tools/bin-assemble/bin-assemble factory_custom.bin \
     0xE8000000 RCW.bin \
     0xE8020000 custom.dtb \
-    0xF6000000 custom_v1_signed.bin \
-    0xF7E00000 iram_Type_A_T1040_r1.0.bin \
-    0xF7F00000 fsl_fman_ucode_t1040.bin \
-    0xF7F40000 wolfboot.bin \
-    0xF7FFC000 stage1/loader_stage1.bin
+    0xEE000000 custom_v1_signed.bin \
+    0xEFE00000 iram_Type_A_T1040_r1.0.bin \
+    0xEFF00000 fsl_fman_ucode_t1040.bin \
+    0xEFF40000 wolfboot.bin \
+    0xEFFFC000 stage1/loader_stage1.bin
 ```
 
 Flash factory_custom.bin to NOR base 0xE800_0000

hal/nxp_ppc.h

@@ -94,7 +94,11 @@
     #endif
 
     #define FLASH_BASE_ADDR      0xEC000000UL
-    #define FLASH_BASE_PHYS_HIGH 0xFULL
+    #ifndef BUILD_LOADER_STAGE1
+    #define FLASH_BASE_PHYS_HIGH 0xFULL /* 36-bit: 0xF_EC000000 */
+    #else
+    #define FLASH_BASE_PHYS_HIGH 0x0ULL /* 32-bit stage1 */
+    #endif
     #define FLASH_LAW_SIZE       LAW_SIZE_64MB
     #define FLASH_TLB_PAGESZ     BOOKE_PAGESZ_64M
 
@@ -110,14 +114,23 @@
     #define CCSRBAR_DEF (0xFE000000) /* T1040RM 4.4.1 default base */
     #define CCSRBAR_SIZE BOOKE_PAGESZ_16M
 
-    #define INITIAL_SRAM_ADDR     0xFDFC0000
-    #define INITIAL_SRAM_LAW_SZ   LAW_SIZE_256KB
-    #define INITIAL_SRAM_LAW_TRGT LAW_TRGT_PSRAM
-    #define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
-
     #define ENABLE_L1_CACHE
     #define ENABLE_INTERRUPTS
 
+    /* T1040 has a 256KB CPC (CoreNet Platform Cache), not PSRAM.
+     * Use L1 locked dcache (16KB) as initial stack, same as T2080.
+     * CPC SRAM is configured but not used for stack to avoid
+     * cold power cycle reliability issues via CoreNet. */
+    #define L1_CACHE_ADDR (0xFDFC0000UL)
+
+    #define L2SRAM_ADDR   (0xFDFE0000UL) /* CPC as SRAM (256KB) */
+    #define L2SRAM_SIZE   (256UL * 1024UL)
+
+    #define INITIAL_SRAM_ADDR     L2SRAM_ADDR
+    #define INITIAL_SRAM_LAW_SZ   LAW_SIZE_256KB
+    #define INITIAL_SRAM_LAW_TRGT LAW_TRGT_DDR_1 /* CPC target per T1040RM */
+    #define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
+
     #ifdef BUILD_LOADER_STAGE1
         #define ENABLE_L2_CACHE
     #else
@@ -131,10 +144,15 @@
     #define DDR_SIZE (8192ULL * 1024ULL * 1024ULL) /* 8GB */
     #endif
 
-    /* 256MB NOR: 0xE8000000 - 0xF7FFFFFF */
+    /* 128MB NOR: 0xE8000000 - 0xEFFFFFFF */
     #define FLASH_BASE_ADDR      0xE8000000UL
-    #define FLASH_BASE_PHYS_HIGH 0xFULL
-    #define FLASH_LAW_SIZE       LAW_SIZE_256MB
+    #ifndef BUILD_LOADER_STAGE1
+    #define FLASH_BASE_PHYS_HIGH 0xFULL /* 36-bit: 0xF_E8000000 */
+    #else
+    #define FLASH_BASE_PHYS_HIGH 0x0ULL /* 32-bit stage1 */
+    #endif
+    #define FLASH_LAW_SIZE       LAW_SIZE_128MB
+    /* e5500 BookE has no 128M page size (64M->256M), use 256M TLB */
     #define FLASH_TLB_PAGESZ     BOOKE_PAGESZ_256M
 
     #define USE_LONG_JUMP

hal/nxp_t1040.ld

@@ -4,15 +4,15 @@ ENTRY( _reset )
 
 MEMORY
 {
-    /* DDR4 - 8GB (offset by destination address and 4KB boot region) */
+    /* DDR4 - 8GB physical (32-bit addressing limits window to <2GB) */
     DRAM (rwx) : ORIGIN = @WOLFBOOT_STAGE1_LOAD_ADDR@,
                  LENGTH = 0x7FFFFFFF - 4K - @WOLFBOOT_STAGE1_LOAD_ADDR@
 
-    /* L1 SRAM - 16KB */
-    L1RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x4000
+    /* L1 locked dcache - 16KB */
+    L1RAM (rwx) : ORIGIN = 0xFDFC0000, LENGTH = 0x4000
 
-    /* Platform SRAM - 160KB */
-    PSRAM (rwx) : ORIGIN = 0xFDFC0000, LENGTH = 0x28000
+    /* CPC SRAM - 256KB */
+    CPCSRAM (rwx) : ORIGIN = 0xFDFE0000, LENGTH = 0x40000
 }
 
 SECTIONS
@@ -84,6 +84,6 @@ SECTIONS
 PROVIDE(_start_heap = _end);
 PROVIDE(_end_stack  = ORIGIN(DRAM) + (LENGTH(DRAM)));
 
-/* Platform SRAM heap/stack */
-/* PROVIDE(_start_heap = ORIGIN(PSRAM)); */
-/* PROVIDE(_end_stack  = ORIGIN(PSRAM) + (LENGTH(PSRAM))); */
+/* CPC SRAM heap/stack (unused - wolfBoot runs from DDR) */
+/* PROVIDE(_start_heap = ORIGIN(CPCSRAM)); */
+/* PROVIDE(_end_stack  = ORIGIN(CPCSRAM) + (LENGTH(CPCSRAM))); */

hal/nxp_t1040_stage1.ld

@@ -2,29 +2,30 @@ OUTPUT_ARCH( "powerpc" )
 
 ENTRY( _reset )
 
-/* Boot ROM out of reset mapped to 0xF7FFF000 */
+/* Boot ROM out of reset mapped to 0xEFFFF000 (top of 128MB NOR) */
 BASE_ADDR = @WOLFBOOT_STAGE1_FLASH_ADDR@;
 
 LOADER_STAGE1_SIZE = @WOLFBOOT_STAGE1_SIZE@;
 
 /* Boot initialization code */
-BOOTSTRAP_TLB = 0xF7FFF000;
+BOOTSTRAP_TLB = 0xEFFFF000;
 
 /* Entry point where RCW directs code to execute from */
-BOOTSTRAP_ENTRY = 0xF7FFFFFC;
+BOOTSTRAP_ENTRY = 0xEFFFFFFC;
 
 MEMORY
 {
     /* Boot Location */
     FLASH (rx) : ORIGIN = BASE_ADDR, LENGTH = LOADER_STAGE1_SIZE
 
-    /* L1 SRAM - 16KB */
-    L1RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x4000
+    /* L1 locked dcache as initial stack - 16KB */
+    L1RAM (rwx) : ORIGIN = 0xFDFC0000, LENGTH = 0x4000
 
-    /* Platform SRAM - 160KB */
-    PSRAM (rwx) : ORIGIN = 0xFDFC0000, LENGTH = 0x28000
+    /* CPC SRAM - 256KB (CoreNet Platform Cache configured as SRAM) */
+    CPCSRAM (rwx) : ORIGIN = 0xFDFE0000, LENGTH = 0x40000
 
-    /* DDR - 8GB: Start at 16MB to avoid using 0x0 (NULL) addresses */
+    /* DDR - 8GB physical, 32-bit addressing limits window to <2GB.
+     * Start at 16MB to avoid using 0x0 (NULL) addresses */
     DRAM (rwx) : ORIGIN = 0x1000000, LENGTH = 0x7FFFFFFF - 0x1000000
 }
 
@@ -105,6 +106,6 @@ SECTIONS
 
 }
 
-/* Platform SRAM heap/stack */
-PROVIDE(_start_heap = ORIGIN(PSRAM));
-PROVIDE(_end_stack  = ORIGIN(PSRAM) + (LENGTH(PSRAM)));
+/* CPC SRAM heap, L1 locked dcache stack */
+PROVIDE(_start_heap = ORIGIN(CPCSRAM));
+PROVIDE(_end_stack  = ORIGIN(L1RAM) + (LENGTH(L1RAM)));

hal/nxp_t10xx.c

@@ -65,9 +65,12 @@
 #endif
 
 #define USE_ERRATA_DDRA008378
-#define USE_ERRATA_DDRA008109
 #define USE_ERRATA_DDRA009663
 #define USE_ERRATA_DDRA009942
+#ifdef TARGET_nxp_t1024
+/* A-008109: T1024 rev 1.0 specific - DDR controller init failure */
+#define USE_ERRATA_DDRA008109
+#endif
 
 /* Forward declarations */
 static void hal_flash_unlock_sector(uint32_t sector);
@@ -525,7 +528,7 @@ enum ifc_amask_sizes {
 
 /* NOR Flash */
 #ifdef TARGET_nxp_t1040
-#define FLASH_BANK_SIZE   (256*1024*1024) /* 256MB NOR */
+#define FLASH_BANK_SIZE   (128*1024*1024) /* 128MB NOR */
 #else
 #define FLASH_BANK_SIZE   (64*1024*1024)  /* 64MB NOR */
 #endif
@@ -1304,7 +1307,7 @@ static void hal_flash_init(void)
                         IFC_CSPR_MSEL_NOR |
                         IFC_CSPR_V));
 #ifdef TARGET_nxp_t1040
-    set32(IFC_AMASK(0), IFC_AMASK_256MB);
+    set32(IFC_AMASK(0), IFC_AMASK_128MB);
 #else
     set32(IFC_AMASK(0), IFC_AMASK_64MB);
 #endif
@@ -1442,10 +1445,13 @@ static void hal_ddr_init(void)
     set32(DDR_DEBUG_29, reg);
 #endif
 
-    /* Wait for data initialization to complete */
+    /* Wait for data initialization to complete.
+     * Use simple delay loop instead of udelay() — timebase may not be
+     * running yet during early stage1 init (RCPM clock distribution). */
     while (get32(DDR_SDRAM_CFG_2) & DDR_SDRAM_CFG_2_D_INIT) {
-        /* busy wait loop - throttle polling */
-        udelay(10000);
+        volatile int i;
+        for (i = 0; i < 1000; i++)
+            ;
     }
 
 #ifdef USE_ERRATA_DDRA009663
@@ -1461,11 +1467,15 @@ void hal_early_init(void)
     /* enable timebase on core 0 */
     set32(RCPM_PCTBENR, (1 << 0));
 
-    /* invalidate the CPC before DDR gets enabled */
+    /* invalidate the CPC before DDR gets enabled.
+     * Skip for stage1: assembly already configured CPC as SRAM and the
+     * stack/heap reside there — re-invalidating would destroy them. */
+#ifndef BUILD_LOADER_STAGE1
     set32((volatile uint32_t*)(CPC_BASE + CPCCSR0),
         (CPCCSR0_CPCFI | CPCCSR0_CPCLFC));
     while (get32((volatile uint32_t*)(CPC_BASE + CPCCSR0)) &
         (CPCCSR0_CPCFI | CPCCSR0_CPCLFC));
+#endif
 
     /* set DCSRCR space = 1G */
     set32(DCFG_DCSR, (get32(DCFG_DCSR) | CORENET_DCSR_SZ_1G));

src/boot_ppc_start.S

@@ -597,8 +597,15 @@ cpc_poll_invalidate:
         stw     r0, CPCSRCR1(r1) /* SRAM high address = 0 */
         /* SRAM low address - use LOAD_ADDR32 on e6500 to avoid sign extension */
         LOAD_ADDR32(r0, L2SRAM_ADDR)
-        /* Enable SRAM and set size (must match L2SRAM_SIZE = 1MB for P384) */
+        /* Enable SRAM and set size.
+         * e6500 (T2080): SRAMSZ_1024 = ways 8-15, 1MB
+         * e5500 (T1040): SRAMSZ_256  = ways 0-7, 256KB
+         * Both are (0x3 << 1) but interpreted differently per core. */
+#ifdef CORE_E6500
         ori     r0, r0, (CPCSRCR0_SRAMSZ_1024 | CPCSRCR0_SRAMEN)
+#else
+        ori     r0, r0, (CPCSRCR0_SRAMSZ_256 | CPCSRCR0_SRAMEN)
+#endif
         stw     r0, CPCSRCR0(r1)
         mbar
         isync

stage1/Makefile

@@ -101,6 +101,7 @@ CFLAGS+=\
 
 # For printf support (disable NO_PRINTF_UART) and increase WOLFBOOT_STAGE1_SIZE
 ifeq ($(ARCH),PPC)
+  CFLAGS+=-g -gdwarf-4
   CFLAGS+=-DNO_PRINTF_UART -DWOLFBOOT_NO_PRINTF
   ifeq ($(NO_XIP),1)
     # Use PIC (Position Independent Code) for first stage loader

test-app/app_nxp_t1040.c

@@ -28,7 +28,7 @@ static const char* hex_lut = "0123456789abcdef";
 void main(void)
 {
     int i = 0;
-    int j = 0;
+    volatile int j = 0;
     int k = 0;
     char snum[8];