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Commit 39e99f0

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dgarskedgarske
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Fixes to get H5 SPI working
1 parent 5ab5722 commit 39e99f0

4 files changed

Lines changed: 39 additions & 40 deletions

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‎hal/spi/spi_drv_stm32.c‎

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,8 @@ void RAMFUNCTION stm_gpio_config(uint32_t base, uint32_t pin, uint32_t mode,
8383

8484
/* Enable GPIO clock */
8585
RCC_GPIO_CLOCK_ER |= (1 << base_num);
86+
/* Delay after an RCC peripheral clock enabling */
87+
reg = RCC_GPIO_CLOCK_ER;
8688

8789
/* Set Mode and Alternate Function */
8890
reg = GPIO_MODE(base) & ~(0x03UL << (pin * 2));
@@ -112,6 +114,10 @@ void RAMFUNCTION stm_gpio_config(uint32_t base, uint32_t pin, uint32_t mode,
112114
/* configure output speed 0=low, 1=med, 2=high, 3=very high */
113115
reg = GPIO_OSPD(base) & ~(0x03UL << (pin * 2));
114116
GPIO_OSPD(base) |= (speed << (pin * 2));
117+
118+
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
119+
120+
#endif
115121
}
116122

117123
#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
@@ -373,7 +379,7 @@ uint8_t RAMFUNCTION spi_read(void)
373379
#ifdef SPI1_RXDR
374380
return SPI1_RXDR;
375381
#else
376-
return SPI1_DR
382+
return SPI1_DR;
377383
#endif
378384
}
379385

@@ -490,10 +496,12 @@ void RAMFUNCTION spi_init(int polarity, int phase)
490496
/* Configure SPI1 for master mode */
491497
SPI1_CR1 &= ~SPI_CR1_SPI_EN;
492498
#if defined(TARGET_stm32h5)
493-
/* baud rate 2 (hclk/8), data size 8 bits, FIFO threshold level (8-data) */
499+
/* baud rate 2 (hclk/8), data size (8-bits), CRC Size (8-bits),
500+
* FIFO threshold level (1-data) */
494501
SPI1_CFG1 = (
495-
((7 & SPI_CFG1_FTHLV_MASK) << SPI_CFG1_FTHLV_SHIFT) |
496502
((2 & SPI_CFG1_BAUDRATE_MASK) << SPI_CFG1_BAUDRATE_SHIFT) |
503+
((7 & SPI_CFG1_CRCSIZE_MASK) << SPI_CFG1_CRCSIZE_SHIFT) |
504+
((0 & SPI_CFG1_FTHLV_MASK) << SPI_CFG1_FTHLV_SHIFT) |
497505
((7 & SPI_CFG1_DSIZE_MASK) << SPI_CFG1_DSIZE_SHIFT));
498506
SPI1_CFG2 = SPI_CRF2_MASTER | SPI_CFG2_SSOE |
499507
(polarity << SPI_CFG2_CLOCK_POL_SHIFT) |

‎hal/spi/spi_drv_stm32.h‎

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,6 @@
2929
#define GPIOC_BASE (0x40020800)
3030
#define GPIOD_BASE (0x40020C00)
3131
#define GPIOE_BASE (0x40021000)
32-
#define GPIO_BASE GPIOA_BASE
3332
#define SPI_GPIO GPIOB_BASE
3433
#define SPI_CS_GPIO GPIOE_BASE
3534
#define SPI_CS_FLASH 1 /* Flash CS connected to GPIOE1 */
@@ -44,9 +43,9 @@
4443
#ifdef TARGET_stm32h5
4544
#include "hal/stm32h5.h"
4645

47-
#define RCC_GPIO_CLOCK_ER RCC_AHB2ENR_CLOCK_ER
4846
#define APB2_CLOCK_RST RCC_APB2_CLOCK_RSTR
4947
#define APB2_CLOCK_ER RCC_APB2_CLOCK_ER
48+
#define RCC_GPIO_CLOCK_ER RCC_AHB2ENR_CLOCK_ER
5049

5150
/* Nucleo STM32H573ZI SPI_A Port (SPI1) */
5251
#define SPI_CLOCK_PIO_BASE GPIOA_BASE
@@ -437,14 +436,15 @@
437436
#define SPI1_TXDR (*(volatile uint8_t *)(SPI1_BASE + 0x20))
438437
#define SPI1_RXDR (*(volatile uint8_t *)(SPI1_BASE + 0x30))
439438

440-
#define SPI_CR1_SPI_EN (1 << 6)
439+
#define SPI_CR1_SPI_EN (1 << 0)
441440
#define SPI_CR1_CSTART (1 << 9) /* Continous start */
441+
442442
#define SPI_CFG1_DSIZE_MASK (0x1F)
443443
#define SPI_CFG1_DSIZE_SHIFT (0)
444-
445444
#define SPI_CFG1_FTHLV_MASK (0x1F)
446445
#define SPI_CFG1_FTHLV_SHIFT (5)
447-
446+
#define SPI_CFG1_CRCSIZE_MASK (0x1F)
447+
#define SPI_CFG1_CRCSIZE_SHIFT (16)
448448
#define SPI_CFG1_BAUDRATE_MASK (0x07)
449449
#define SPI_CFG1_BAUDRATE_SHIFT (28)
450450

@@ -458,8 +458,8 @@
458458
#define SPI_CFG2_COMM_MASK (0x3) /* 0=full duplex, 1=simplex tx, 2=simplex rx, 3=half duplex */
459459
#define SPI_CFG2_COMM_SHIFT (17)
460460

461-
#define SPI_SR_RX_NOTEMPTY (1 << 0)
462-
#define SPI_SR_TX_EMPTY (1 << 1)
461+
#define SPI_SR_RX_NOTEMPTY (1UL << 0)
462+
#define SPI_SR_TX_EMPTY (1UL << 1)
463463

464464
#else
465465

@@ -499,6 +499,9 @@
499499
#define GPIO_BSRR(base) (*(volatile uint32_t *)(base + 0x18)) /* GPIOx_BSRR */
500500
#define GPIO_AFL(base) (*(volatile uint32_t *)(base + 0x20)) /* GPIOx_AFRL */
501501
#define GPIO_AFH(base) (*(volatile uint32_t *)(base + 0x24)) /* GPIOx_AFRH */
502+
#ifndef GPIO_SECCFGR
503+
#define GPIO_SECCFGR(base) (*(volatile uint32_t *)(base + 0x30)) /* GPIOx_SECCFGR */
504+
#endif
502505

503506
#define GPIO_MODE_INPUT (0)
504507
#define GPIO_MODE_OUTPUT (1)

‎hal/stm32h5.c‎

Lines changed: 15 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -272,24 +272,25 @@ static void clock_pll_off(void)
272272

273273
}
274274

275-
/*This implementation will setup MSI 48 MHz as PLL Source Mux, PLLCLK as System Clock Source*/
275+
/* If PLL_SRC_HSE is set then HSE (8MHz) is used otherwise HSI 64 MHz is used
276+
* and system clock is 250MHz */
276277

277278
static void clock_pll_on(void)
278279
{
279280
uint32_t reg32;
280281
uint32_t plln, pllm, pllq, pllp, pllr, hpre, apb1pre, apb2pre, apb3pre, flash_waitstates;
281282

282283
#if PLL_SRC_HSE
283-
pllm = 4;
284-
plln = 250;
285-
pllp = 2;
286-
pllq = 2;
284+
pllm = 1;
285+
plln = 62;
286+
pllp = 2; /* 250Mhz */
287+
pllq = 5; /* 100Mhz */
287288
pllr = 2;
288289
#else
289-
pllm = 1;
290-
plln = 129;
290+
pllm = 4;
291+
plln = 31;
291292
pllp = 2;
292-
pllq = 2;
293+
pllq = 5;
293294
pllr = 2;
294295
#endif
295296
flash_waitstates = 5;
@@ -432,8 +433,8 @@ static void periph_unsecure(void)
432433
volatile uint32_t *nvic_itns;
433434
uint32_t nvic_reg_pos, nvic_reg_off;
434435

435-
/*Enable clock for User LED GPIOs */
436-
RCC_AHB2_CLOCK_ER|= LED_AHB2_ENABLE;
436+
/* Enable clock for User LED GPIOs */
437+
RCC_AHB2_CLOCK_ER |= LED_AHB2_ENABLE;
437438

438439
/* Enable GPIO clock for accessing SECCFGR registers */
439440
RCC_AHB2_CLOCK_ER |= GPIOA_AHB2_CLOCK_ER;
@@ -449,10 +450,10 @@ static void periph_unsecure(void)
449450

450451

451452
PWR_CR2 |= PWR_CR2_IOSV;
452-
/*Un-secure User LED GPIO pins */
453-
GPIO_SECCFGR(GPIOG_BASE) &= ~(1 << 4);
454-
GPIO_SECCFGR(GPIOB_BASE) &= ~(1 << 0);
455-
GPIO_SECCFGR(GPIOF_BASE) &= ~(1 << 4);
453+
/* Un-secure User LED GPIO pins */
454+
GPIO_SECCFGR(GPIOG_BASE) &= ~(1 << LED_BOOT_PIN); /* PG4 - Nucleo board - Orange Led */
455+
GPIO_SECCFGR(GPIOB_BASE) &= ~(1 << LED_USR_PIN); /* PB0 - Nucleo board - Green Led */
456+
GPIO_SECCFGR(GPIOF_BASE) &= ~(1 << LED_EXTRA_PIN); /* PF4 - Nucleo board - Blue Led */
456457

457458
/* Unsecure LPUART1 */
458459
GPIO_SECCFGR(GPIOB_BASE) &= ~(1<<UART1_TX_PIN);
@@ -478,17 +479,6 @@ static void periph_unsecure(void)
478479
nvic_reg_off = NVIC_USART3_IRQ % 32;
479480
nvic_itns = ((volatile uint32_t *)(NVIC_ITNS_BASE + 4 * nvic_reg_pos));
480481
*nvic_itns |= (1 << nvic_reg_off);
481-
482-
483-
/* Disable GPIOs clock used previously for accessing SECCFGR registers */
484-
#if 0
485-
RCC_AHB2_CLOCK_ER &= ~GPIOA_AHB2_CLOCK_ER;
486-
RCC_AHB2_CLOCK_ER &= ~GPIOB_AHB2_CLOCK_ER;
487-
RCC_AHB2_CLOCK_ER &= ~GPIOC_AHB2_CLOCK_ER;
488-
RCC_AHB2_CLOCK_ER &= ~GPIOD_AHB2_CLOCK_ER;
489-
#endif
490-
491-
492482
}
493483
#endif
494484

‎test-app/app_stm32h5.c‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -150,9 +150,6 @@ void extra_led_off(void)
150150
GPIOF_BSRR |= (1 << (LED_EXTRA_PIN + 16));
151151
}
152152

153-
static char CaBuf[2048];
154-
static uint8_t my_pubkey[200];
155-
156153
extern int ecdsa_sign_verify(int devId);
157154

158155
/* Command line commands */
@@ -545,9 +542,10 @@ static int cmd_timestamp(const char *args)
545542
{
546543
struct timespec tp = {};
547544
clock_gettime(0, &tp);
548-
printf("Current timestamp: %llu.%03lu\r\n", tp.tv_sec, tp.tv_nsec/1000000);
545+
printf("Current timestamp: %lu.%03lu\r\n",
546+
(long unsigned int)tp.tv_sec, tp.tv_nsec/1000000);
549547
printf("Current systick: %u\r\n", jiffies);
550-
printf("VTOR: %08lx\r\n", (*(volatile uint32_t *)(0xE000ED08)));
548+
printf("VTOR: 0x%08lx\r\n", (*(volatile uint32_t *)(0xE000ED08)));
551549
return 0;
552550
}
553551

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