wolfBoot/config/examples/nxp-s32k142.config at master · wolfSSL/wolfBoot · GitHub

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# wolfBoot configuration for NXP S32K142
#
# S32K142: Cortex-M4F, 256KB Flash, 32KB SRAM
# Flash sector size: 2KB
# Default: RUN mode at 48 MHz (FIRC - internal RC oscillator)
#
# Build: cp config/examples/nxp-s32k142.config .config && make

ARCH?=ARM
CORTEX_M4?=1
NO_MPU=1
TARGET?=s32k1xx
SIGN?=ECC256
HASH?=SHA256
VTOR?=1
NO_ASM?=0
EXT_FLASH?=0
SPI_FLASH?=0
ALLOW_DOWNGRADE?=0

# S32K1xx flash requires erase before write (cannot re-program same location)
# This is required for sector swap trailer flag updates to work correctly
NVM_FLASH_WRITEONCE?=1

WOLFBOOT_VERSION?=0
V?=0
SPMATH?=1
RAM_CODE?=1
DUALBANK_SWAP?=0

# 2KB sectors (S32K142 only - larger variants use 4KB sectors)
WOLFBOOT_SECTOR_SIZE?=0x800

# Memory layout for S32K142 (256KB Flash):
#   Bootloader:       0x00000000 - 0x0000BFFF (48 KB)
#   Boot Partition:   0x0000C000 - 0x00024FFF (100 KB)
#   Update Partition: 0x00025000 - 0x0003DFFF (100 KB)
#   Swap Sector:      0x0003E000 - 0x0003E7FF (2 KB)
WOLFBOOT_PARTITION_SIZE?=0x19000
WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xC000
WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x25000
WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x3E000

# Clock mode: Default is RUN mode with FIRC (48 MHz internal RC)
# To enable HSRUN mode (112 MHz), uncomment below (requires SOSC + SPLL, not fully implemented):
#CFLAGS_EXTRA+=-DS32K1XX_CLOCK_HSRUN

# Optionally enable watchdog
#CFLAGS_EXTRA+=-DWATCHDOG

# Flash Option Byte (FOPT) override (default 0xFF)
# Example: disable RESET_PIN_CFG (use PTA5 as GPIO instead of RESET)
#CFLAGS_EXTRA+=-DWOLFBOOT_FOPT=0xF7

# Debugging options (uncomment as needed)
DEBUG?=0
DEBUG_SYMBOLS?=0
DEBUG_UART?=0
#CFLAGS_EXTRA+=-DDEBUG_HARDFAULT