Merge pull request #419 from sbutz/stimecmp

riscv: Add stimecmp CSR

Author: romancardenas

riscv/CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
+- Add `stimecmp`/`stimecmph` CSRs
 - Add `tselect`, `tdata2` and `tdata3` Sdtrig CSRs as raw `read_write_csr_as_usize!` accessors, and `tdata1` and `tcontrol` as typed CSRs with field accessors.
 - Add `read_bits`/`try_read_bits` and `write_bits`/`try_write_bits` to the modules generated by `read_csr_as_usize!` and `write_csr_as_usize!`, as aliases of `read`/`write` so that a generated CSR module offers the same raw accessors no matter which macro defined it.
 - Add `read_bits`/`try_read_bits` and `write_bits`/`try_write_bits` to the CSR modules generated by `read_write_csr!` `read_only_csr!` and `write_only_csr!`.

riscv/src/register.rs

@@ -134,6 +134,11 @@ pub mod miselect;
 pub mod sireg;
 pub mod siselect;
 
+// Supervisor timer interrupts
+pub mod stimecmp;
+#[cfg(any(test, target_arch = "riscv32"))]
+pub mod stimecmph;
+
 // Virtual supervisor indirect access
 pub mod vsiselect;
 

riscv/src/register/stimecmp.rs

@@ -0,0 +1,6 @@
+//! stimecmp register
+
+read_csr_as_usize!(0x14D);
+write_csr_as_usize!(0x14D);
+read_composite_csr!(super::stimecmph::read(), read());
+write_composite_csr!(super::stimecmph::write, write);

riscv/src/register/stimecmph.rs

@@ -0,0 +1,4 @@
+//! stimecmph register
+
+read_csr_as_usize_rv32!(0x15D);
+write_csr_as_usize_rv32!(0x15D);