style: format code with clang-format [skip ci]

Author: moment-NEW

bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.c

@@ -16,7 +16,7 @@
 #include "drv_dma.h"
 
 // #define DRV_DEBUG
-#define LOG_TAG             "drv.dma"
+#define LOG_TAG "drv.dma"
 #include <drv_log.h>
 /*
  * DMA-capable BSPs are expected to enable HAL_DMA_MODULE_ENABLED in the
@@ -86,12 +86,9 @@ static void stm32_dma_enable_clock(rt_uint32_t dma_rcc, rt_bool_t is_bdma)
  * DMA client does not disable a line still used by another active client.
  * All other DMA IRQs keep the direct enable/disable behavior.
  */
-#if (defined(SOC_SERIES_STM32F1) && defined(DMA2_Channel4_5_IRQn)) \
- || (defined(SOC_SERIES_STM32L0) && defined(DMA1_Channel4_5_6_7_IRQn)) \
- || (defined(SOC_SERIES_STM32G0) && defined(DMA1_Channel2_3_IRQn)) \
- || (defined(SOC_SERIES_STM32F0) && (defined(DMA1_Channel2_3_IRQn) || defined(DMA1_Channel4_5_IRQn) || defined(DMA1_Channel4_5_6_7_IRQn)))
+#if (defined(SOC_SERIES_STM32F1) && defined(DMA2_Channel4_5_IRQn)) || (defined(SOC_SERIES_STM32L0) && defined(DMA1_Channel4_5_6_7_IRQn)) || (defined(SOC_SERIES_STM32G0) && defined(DMA1_Channel2_3_IRQn)) || (defined(SOC_SERIES_STM32F0) && (defined(DMA1_Channel2_3_IRQn) || defined(DMA1_Channel4_5_IRQn) || defined(DMA1_Channel4_5_6_7_IRQn)))
 #define STM32_DMA_HAS_SHARED_IRQ_REFCNT
-#define STM32_DMA_IRQ_SLOT_COUNT    ((rt_uint32_t)(sizeof(NVIC->ISER) / sizeof(NVIC->ISER[0]) * 32U))
+#define STM32_DMA_IRQ_SLOT_COUNT ((rt_uint32_t)(sizeof(NVIC->ISER) / sizeof(NVIC->ISER[0]) * 32U))
 
 /**
  * @brief Reference count for each shared DMA IRQ line.
@@ -139,24 +136,24 @@ static rt_bool_t stm32_dma_irq_needs_refcount(IRQn_Type dma_irq)
 #endif /* defined(SOC_SERIES_STM32G0) && defined(DMA1_Channel2_3_IRQn) */
 
 #if defined(SOC_SERIES_STM32F0)
-# if defined(DMA1_Channel2_3_IRQn)
+#if defined(DMA1_Channel2_3_IRQn)
     if (dma_irq == DMA1_Channel2_3_IRQn)
     {
         return RT_TRUE;
     }
-# endif /* defined(DMA1_Channel2_3_IRQn) */
-# if defined(DMA1_Channel4_5_IRQn)
+#endif /* defined(DMA1_Channel2_3_IRQn) */
+#if defined(DMA1_Channel4_5_IRQn)
     if (dma_irq == DMA1_Channel4_5_IRQn)
     {
         return RT_TRUE;
     }
-# endif /* defined(DMA1_Channel4_5_IRQn) */
-# if defined(DMA1_Channel4_5_6_7_IRQn)
+#endif /* defined(DMA1_Channel4_5_IRQn) */
+#if defined(DMA1_Channel4_5_6_7_IRQn)
     if (dma_irq == DMA1_Channel4_5_6_7_IRQn)
     {
         return RT_TRUE;
     }
-# endif /* defined(DMA1_Channel4_5_6_7_IRQn) */
+#endif /* defined(DMA1_Channel4_5_6_7_IRQn) */
 #endif /* defined(SOC_SERIES_STM32F0) */
 
     return RT_FALSE;