AMD Zen 5 Support

[MaoxinYee]

Why do you need support for this specific architecture?
AMD Zen 5 CPU are widely used in laptops and desktops.

Which architecture model, family and further information? CPU or accelerator?

AMD Ryzen AI MAX+ 395 CPU
processor : 31
vendor_id : AuthenticAMD
cpu family : 26
model : 112
model name : AMD RYZEN AI MAX+ 395 w/ Radeon 8060S
stepping : 0
microcode : 0xb70001e

Is the documentation of the hardware counters publicly available?

Please check the vendor webpages for the documentation. It should contain the infos for hardware performance counting.

Are there already any usable tools (commercial or open-source)?

No

Can the LIKWID team get remote access to the machine or a system of the same type?

If your team need to get remote access, I can provide some support to access my machine.

Attachments

Please attach the outputs of /proc/cpuinfo and ls /sys/devices as files to the issue.

processor : 31
vendor_id : AuthenticAMD
cpu family : 26
model : 112
model name : AMD RYZEN AI MAX+ 395 w/ Radeon 8060S
stepping : 0
microcode : 0xb70001e
cpu MHz : 2000.000
cache size : 1024 KB
physical id : 0
siblings : 32
core id : 15
cpu cores : 16
apicid : 31
initial apicid : 31
fpu : yes
fpu_exception : yes
cpuid level : 16
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good amd_lbr_v2 nopl xtopology nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba perfmon_v2 ibrs ibpb stibp ibrs_enhanced vmmcall fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local user_shstk avx_vnni avx512_bf16 clzero irperf xsaveerptr rdpru wbnoinvd cppc arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif x2avic v_spec_ctrl vnmi avx512vbmi umip pku ospke avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq rdpid bus_lock_detect movdiri movdir64b overflow_recov succor smca fsrm avx512_vp2intersect flush_l1d amd_lbr_pmc_freeze
bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass srso
bogomips : 5988.76
TLB size : 192 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 48 bits physical, 48 bits virtual
power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14]

[MaoxinYee]

devices.txt
cpuinfo.txt

[TomTheBear]

Unfortunately, no docs available yet.

Have your tried the Zen5 PR on your machine with changed Zen5 model ID (#define ZEN5_EPYC 0x70 in src/includes/topology.h)? My guess is that the hwthread-local counters are the same. They might differ in the provided Uncore units. The provided devices.txt contains only the hwthread-local unit (cpu) and the RAPL energy unit (power), not the uncore devices (amd_df and amd_umc_*).

Your devices.txt shows a power_core unit. Can you please provide the filenames and their content in /sys/devices/power_core/events and /sys/devices/power_core/format. If there is a cpulist or cpumask file in the unit folder, this one as well.

[MaoxinYee]

Yes, I have tried the Zen5 PR on my machine,but it still failed to run. Thank you, I will try the changed code again.

[MaoxinYee]

(ironenv) ymx@link:~/likwid$ cd /sys/devices/power_core/events
(ironenv) ymx@link:/sys/devices/power_core/events$ ls
energy-core energy-core.scale energy-core.unit
(ironenv) ymx@link:/sys/devices/power_core/events$ cat energy-core
event=0x01
(ironenv) ymx@link:/sys/devices/power_core/events$ cat energy-core.scale
2.3283064365386962890625e-10
(ironenv) ymx@link:/sys/devices/power_core/events$ cat energy-core.unit
Joules

[MaoxinYee]

(ironenv) ymx@link:~$ cd /sys/devices/power_core/format
(ironenv) ymx@link:/sys/devices/power_core/format$ ls
event
(ironenv) ymx@link:/sys/devices/power_core/format$ cat event
config:0-7

[MaoxinYee]

Thanks, Just put the code of your Zen5 CPU modelID on the #define ZEN5_EPYC 0x70 in src/includes/topology.h.
Then It works!

[TomTheBear]

This was just a test. For general support, the architectures needs to be added to the topology code. It is not a big deal but until I know which units are supported and whether there is any difference to the 0x2 Zen5 models, I refrain from adding it.

The power_core perf_event unit is definitely new but might be available for 0x2 Zen5 models as well with more recent kernels.

I leave the issue open as a reminder to check AMD Tech docs regularly.