graph LR
Chip_Model_Manager["Chip Model Manager"]
CPUID_Data_Reader["CPUID Data Reader"]
Register_Definition_Refiner["Register Definition Refiner"]
Generator["Generator"]
Read_Encoded_File["Read Encoded File"]
Read_XED_Database["Read XED Database"]
Chip_Model_Manager -- "provides validated CPU chip definition data to" --> Generator
Chip_Model_Manager -- "provides CPU chip definition data to" --> Read_Encoded_File
CPUID_Data_Reader -- "supplies structured CPUID data to" --> Generator
CPUID_Data_Reader -- "supplies structured CPUID data to" --> Read_XED_Database
Register_Definition_Refiner -- "provides refined register data to" --> Generator
The core of this subsystem revolves around the processing and generation of CPU-related data. The Chip Model Manager serves as the central authority for CPU chip definitions, validating and expanding this data. The CPUID Data Reader specializes in extracting and structuring raw CPUID information, while the Register Definition Refiner standardizes register definitions. These three components (Chip Model Manager, CPUID Data Reader, and Register Definition Refiner) act as primary data providers, feeding their processed information to the Generator. The Generator then synthesizes this diverse input into various output formats, such as instruction tables and enumerations. Additionally, the Chip Model Manager supplies CPU chip definition data to Read Encoded File for instruction parsing, and the CPUID Data Reader provides structured CPUID data to Read XED Database for comprehensive instruction set information. This architecture ensures a clear flow from raw data acquisition and refinement to the generation of structured, usable output for further system operations.
Acts as the authoritative source for CPU capabilities. It parses, expands, and validates CPU chip definitions from external sources, managing feature indices and ensuring consistency across instruction sets. This component is crucial for defining the target CPU's supported features.
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Specializes in loading, parsing, and providing programmatic access to raw CPUID records and group information. It transforms unstructured CPUID strings into a structured, queryable format, making CPU feature detection efficient.
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Focuses on processing and refining raw register definitions. It organizes and standardizes register information into a usable format, abstracting away low-level representation details for other components.
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Responsible for generating various output files, including instruction tables, enumerations, and other derived data structures, based on the processed CPU and register definitions. It acts as the final stage in data transformation for consumption by other parts of the system or external tools.
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Handles the parsing and interpretation of encoded instruction files. It reads and decodes the raw instruction data, making it available for further processing and validation within the system.
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Manages the loading and access to the XED (X86 Encoder Decoder) instruction database. It provides structured access to the comprehensive instruction set information, which is critical for accurate instruction decoding and encoding.
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